ST STM32L4+ Series Reference Manual page 2135

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56.15.10 OTG status read and pop registers (OTG_GRXSTSP)

Address offset for pop: 0x020

Reset value: 0x0000 0000

This description is for register OTG_GRXSTSP in Device mode.

Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the

contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and

pop register) additionally pops the top data entry out of the Rx FIFO.

The core ignores the receive status pop/read when the receive FIFO is empty and returns a

value of 0x0000 0000. The application must only pop the receive status FIFO when the

receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 STSPHST: Status phase start

Bits 26:25 Reserved, must be kept at reset value.

Bits 24:21 FRMNUM[3:0]: Frame number

Bits 20:17 PKTSTS[3:0]: Packet status

Bits 16:15 DPID[1:0]: Data PID

Bits 14:4 BCNT[10:0]: Byte count

Bits 3:0 EPNUM[3:0]: Endpoint number

Indicates the start of the status phase for a control write transfer. This bit is set along with

the OUT transfer completed PKTSTS pattern.

This is the least significant 4 bits of the frame number in which the packet is received on the

USB. This field is supported only when isochronous OUT endpoints are supported.

Indicates the status of the received packet

0001: Global OUT NAK (triggers an interrupt)

0010: OUT data packet received

0011: OUT transfer completed (triggers an interrupt)

0100: SETUP transaction completed (triggers an interrupt)

0110: SETUP data packet received

Others: Reserved

Indicates the data PID of the received OUT data packet

Indicates the byte count of the received data packet.

Indicates the endpoint number to which the current received packet belongs.

USB on-the-go full-speed (OTG_FS)

RM0432 Rev 6

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