Advertisement
RM0432
56.15.8
OTG receive status debug read register (OTG_GRXSTSR)
Address offset for read: 0x01C
Reset value: 0x0000 0000
This description is for register OTG_GRXSTSR in Device mode.
A read to the receive status debug read register returns the contents of the top of the
receive FIFO.
The core ignores the receive status read when the receive FIFO is empty and returns a
value of 0x0000 0000.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
DPID[0]
r
r
r
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 STSPHST: Status phase start
Bits 26:25 Reserved, must be kept at reset value.
Bits 24:21 FRMNUM[3:0]: Frame number
Bits 20:17 PKTSTS[3:0]: Packet status
Bits 16:15 DPID[1:0]: Data PID
Bits 14:4 BCNT[10:0]: Byte count
Bits 3:0 EPNUM[3:0]: Endpoint number
28
27
26
25
STSPH
Res.
Res.
ST
r
12
11
10
9
BCNT[10:0]
r
r
r
r
Indicates the start of the status phase for a control write transfer. This bit is set along with
the OUT transfer completed PKTSTS pattern.
This is the least significant 4 bits of the frame number in which the packet is received on the
USB. This field is supported only when isochronous OUT endpoints are supported.
Indicates the status of the received packet
0001: Global OUT NAK (triggers an interrupt)
0010: OUT data packet received
0011: OUT transfer completed (triggers an interrupt)
0100: SETUP transaction completed (triggers an interrupt)
0110: SETUP data packet received
Others: Reserved
Indicates the data PID of the received OUT data packet
00: DATA0
10: DATA1
Indicates the byte count of the received data packet.
Indicates the endpoint number to which the current received packet belongs.
USB on-the-go full-speed (OTG_FS)
24
23
22
FRMNUM[3:0]
r
r
r
8
7
6
r
r
r
RM0432 Rev 6
21
20
19
18
PKTSTS[3:0]
r
r
r
r
5
4
3
2
EPNUM[3:0]
r
r
r
r
17
16
DPID[1]
r
r
1
0
r
r
2133/2301
2245
Advertisement
Need help?
Do you have a question about the STM32L4+ Series and is the answer not in the manual?