ST STM32L4+ Series Reference Manual page 2136

USB on-the-go full-speed (OTG_FS)
56.15.11 OTG status read and pop registers [alternate] (OTG_GRXSTSP)
Address offset for pop: 0x020
Reset value: 0x0000 0000
This description is for register OTG_GRXSTSP in Host mode.
Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the
contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and
pop register) additionally pops the top data entry out of the Rx FIFO.
The core ignores the receive status pop/read when the receive FIFO is empty and returns a
value of 0x0000 0000. The application must only pop the receive status FIFO when the
receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is
asserted.
31 30 29
Res. Res. Res. Res.
15 14 13
DPID
r r r
Bits 31:21 Reserved, must be kept at reset value.
Bits 20:17 PKTSTS[3:0]: Packet status
Bits 16:15 DPID[1:0]: Data PID
Bits 14:4 BCNT[10:0]: Byte count
Bits 3:0 CHNUM[3:0]: Channel number
2136/2301
28 27 26 25
Res. Res. Res.
12 11 10 9
BCNT[10:0]
r r r r
Indicates the status of the received packet
0010: IN data packet received
0011: IN transfer completed (triggers an interrupt)
0101: Data toggle error (triggers an interrupt)
0111: Channel halted (triggers an interrupt)
Others: Reserved
Indicates the data PID of the received packet
00: DATA0
10: DATA1
Indicates the byte count of the received IN data packet.
Indicates the channel number to which the current received packet belongs.
24 23 22
Res. Res. Res.
8 7 6
r r r
RM0432 Rev 6
21 20 19 18
Res. PKTSTS[3:0]
r r r
5 4 3 2
CHNUM[3:0]
r r r r
RM0432
17 16
DPID
r r
1 0
r r