ST STM32L4+ Series Reference Manual page 2122

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USB on-the-go full-speed (OTG_FS)

OTG USB configuration register (OTG_GUSBCFG)

Address offset: 0x00C

Reset value: 0x0000 1440

This register can be used to configure the core after power-on or a changing to host mode

or device mode. It contains USB and USB-PHY related configuration parameters. The

application must program this register before starting any transactions on either the AHB or

the USB. Do not make changes to this register after the initial programming.

Bit 31 Reserved, must be kept at reset value.

Bit 30 FDMOD: Force device mode

Writing a 1 to this bit, forces the core to device mode irrespective of the OTG_ID input pin.

0: Normal mode

1: Force device mode

After setting the force bit, the application must wait at least 25 ms before the change takes

Note: Accessible in both device and host modes.

Bit 29 FHMOD: Force host mode

Writing a 1 to this bit, forces the core to host mode irrespective of the OTG_ID input pin.

0: Normal mode

1: Force host mode

After setting the force bit, the application must wait at least 25 ms before the change takes

Note: Accessible in both device and host modes.

Bits 28:26 Reserved, must be kept at reset value.

Bits 25:23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

Bits 21:16 Reserved, must be kept at reset value.

Bit 15 Reserved, must be kept at reset value.

Bit 14 Reserved, must be kept at reset value.

Bits 13:10 TRDT[3:0]: USB turnaround time

These bits allows to set the turnaround time in PHY clocks. They must be configured

according to

Higher TRDT values allow stretching the USB response time to IN tokens in order to

compensate for longer AHB read access latency to the data FIFO.

Note: Only accessible in device mode.

Table 421: TRDT values

(FS), depending on the application AHB frequency.

RM0432 Rev 6

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