ST STM32L4+ Series Reference Manual page 2148

USB on-the-go full-speed (OTG_FS)
56.15.21 OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx)
Address offset: 0x104 + 0x04 * (x - 1), (x = 1 to 5)
Reset value: Block 1: 0x0200 0400
Reset value: Block 2: 0x0200 0600
Reset value: Block 3: 0x0200 0800
Reset value: Block 4: 0x0200 0A00
Reset value: Block 5: 0x0200 0C00
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:16 INEPTXFD[15:0]: IN endpoint Tx FIFO depth
Bits 15:0 INEPTXSA[15:0]: IN endpoint FIFOx transmit RAM start address
56.15.22 Host-mode registers
Bit values in the register descriptions are expressed in binary unless otherwise specified.
Host-mode registers affect the operation of the core in the host mode. Host mode registers
must not be accessed in device mode, as the results are undefined. Host mode registers
can be categorized as follows:
56.15.23 OTG host configuration register (OTG_HCFG)
Address offset: 0x400
Reset value: 0x0000 0000
This register configures the core after power-on. Do not make changes to this register after
initializing the host.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
2148/2301
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
This value is in terms of 32-bit words.
Minimum value is 16
This field contains the memory start address for IN endpoint transmit FIFOx. The address
must be aligned with a 32-bit memory location.
28 27 26 25
Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
INEPTXFD[15:0]
rw rw rw
8 7 6
INEPTXSA[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. FSLSS
r
RM0432
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
FSLSPCS[1:0]
rw rw