Pin Configuration And 7.1 Pin Diagram - Mot Package (Top View) - Texas Instruments SimpleLink CC1312PSIP Manual

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7 Pin Configuration and Functions
7.1 Pin Diagram – MOT Package (Top View)
DIO_26
DIO_27
DIO_28
nRESET
GND
NC
DIO_29
DIO_30
GND
GND
GND
GND
GND
Figure 7-1. MOT (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in
• Pin 23, DIO_5
• Pin 24, DIO_6
• Pin 25, DIO_7
• Pin 34, JTAG_TMSC
• Pin 36, DIO_16
• Pin 37, DIO_17
The following I/O pins marked in
• Pin 1, DIO_26
• Pin 2, DIO_27
• Pin 3, DIO_28
• Pin 7, DIO_29
• Pin 8, DIO_30
• Pin 44, DIO_23
• Pin 45, DIO_24
• Pin 48, DIO_25
Copyright © 2023 Texas Instruments Incorporated
1
2
3
CC1312PSIP
4
5 49 50
54 55
6
7 59 60
8
64 65
9 69 70
10
11
12
13
Figure 7-1 in bold have high-drive capabilities:
Figure 7-1 in italics have analog capabilities:
Product Folder Links:
51 52 53
56 57 58
61 62 63
66 67 68
71 72 73
CC1312PSIP
CC1312PSIP
SWRS293 – NOVEMBER 2023
37
DIO_17
36
DIO_16
35
JTAG_TCKC
34
JTAG_TMSC
33
DIO_15
32
DIO_14
31
DIO_13
30
DIO_12
29
DIO_11
28
DIO_10
27
DIO_9
26
DIO_8
25
DIO_7
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