Tps7H4003Evm Default Configuration; Table 2-1. Default Evm Configuration - Texas Instruments TPS7H4003EVM User Manual

TPS7H4003EVM Default Configuration

2 TPS7H4003EVM Default Configuration
Table 2-1 describes the default configuration of the TPS7H4003EVM listing the external components that define
the converter design.
PARAMETER
Input power supply
Regulated output voltage
L
OUT
C
OUT
Output current
Switching frequency
Soft start time constant
UVLO enable rising
UVLO enable falling
Loop bandwidth
Loop phase margin
Gain margin
4 TPS7H4003EVM Evaluation Module (EVM)

Table 2-1. Default EVM Configuration

SPECIFICATIONS
5 V
1 V
1.0 µH
2 mF value used during single event effects testing ensuring regulation
0 to 18 A
500 kHz
≈2 ms
≈4.432 V
≈4.284 V
≈30 kHz
Set by operational transconductance amplifier (OTA) compensation
≈60° circuit: R7 (RCOMP) = 10 kΩ, C15 (CCOMP) = 10 nF, C14 (CHF) =
≈–25 dB
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DESCRIPTION
Bound by UVLO enable circuit (R9, R10)
R6 (RTOP) = 10 kΩ, R7 (RBOTTOM) = 15.4 kΩ
Chosen to meet inductor ripple current of 10% (Kind = 0.1)
Chosen for (1) ESR = 1 mΩ to set output voltage ripple; (2)
maintained with single event upset to switching
By design
Set by R1 (RT) = 174 kΩ
Set by C16 (Css) = 10 nF
Set by R10 = 10 kΩ and R9 = 3.4 kΩ
Set by R10 = 10 kΩ and R9 = 3.4 kΩ
150 pF
SLVUC73A – JANUARY 2022 – REVISED AUGUST 2023
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