Static Nvm Settings; Application-Based Configuration Settings - Texas Instruments TPS65941213-Q1 User Manual

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TPS65941111-Q1 BUCK1-4
(PMIC-B)
BUCK5
LDO1
LDO2
LDO3
LDO4
TPS22965W-Q1 Ld Sw A
TPS22965W-Q1 Ld Sw B
TPS62813-Q1 Buck A
TLV73318P-Q1 LDO-A
1. Rail Group settings for the TPS65941213-Q1 and TPS65941111-Q1 are found in
2. Power rails VDD_DDR_1V1 and VDD1_LPDDR4_1V8 are safety critical but do not required direct voltage
or current monitoring since other means are available (for example, SoC internal timeout gaskets and ECC
checkers) provide diagnostic coverage to detect faults in the DDR voltage.
3. Power rails VDD_IO_1V8/3V3 is typically not safety critical since other means are available (for example,
black-channel checkers) to provide diagnostic coverage to detect faults in SoC signaling interfaces (for
example, CAN, UART, and SPI).
4. If an SoC GPIO control signal is used in a safety critical interface, then adding voltage and current
monitoring to specific VIO power rail may be needed per customer's end product design.
5. PMIC resource, FB_B3 is used to monitor both OV and UV of VDD_MCUIO_3V3. This PMIC monitor is
associated with the MCU power group, and can be updated during run time.
6. Power rail VPP_EFUSE_1V8 is not safety critical since Efuse programming does not occur during safety
critical processing.
7. PMIC-B, Buck3 and 4 have unused remote sense feedback inputs that can be assigned to provide OV and
UV voltage monitoring after SoC SW boot for 2x external power rails per desired functional safety needs.
Optional OV/UV monitoring of VDD_DDR_1V1 and VDD_IO_3V3 power rails are examples.

5 Static NVM Settings

The TPS6594-Q1 devices consist of user register space and an NVM. The settings in NVM, which are loaded
into the user registers during the transition from INIT to BOOT BIST, are provided in this section. Note: The user
registers can be changed during state transitions, such as moving from STANDBY to ACTIVE mode. The user
register map is described in the TPS6594-Q1 datasheet.

5.1 Application-Based Configuration Settings

In the TPS6594-Q1 datasheet, there are seven application-based configurations for each BUCK to operate
within. The following list includes the different configurations available:
• 2.2 MHz Single Phase for DDR Termination
• 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase
• 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only
• 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only
• 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase
• 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only
• 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only
SLVUC99A – JANUARY 2022 – REVISED JANUARY 2022
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Table 4-2. Power Monitoring Safety Features (continued)
VDD_CORE_0V8 SOC
VDD_RAM_0V85 SOC
VDD_SD_DV SOC
VDA_USB_3V3 SOC
VDD_IO_1V8 SOC
VDA_PLL_1V8 SOC
VDD_MCUIO_3V3 MCU
VDD_IO_3V3 SOC
VDD_LPDDR4_1 None
V1
VDD_EFUSE_1V8 None
Copyright © 2022 Texas Instruments Incorporated
ASIL-B ASIL-D Adds
PMIC-B - OV & PMIC-B -CM
UV
PMIC-B - OV & PMIC-B -CM
UV
PMIC-B - OV & PMIC-B -CM
UV
PMIC-B - OV & PMIC-B -CM
UV
PMIC-B - OV & PMIC-B -CM
UV
PMIC-B - OV & PMIC-B -CM
UV
PMIC-A (FB_B3) - NA4
OV & UV5
PMIC-B (FB_B4) - NA3 4
OV & UV7
SoC2 NA2 7
NA6 NA6
Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for
Static NVM Settings
PMIC-B -RVM
PMIC-B -RVM
PMIC-B -RVM
PMIC-B -RVM
PMIC-B -RVM
PMIC-B -RVM
Table 5-7.
Jacinto™ 7 J721E, PDN-0C
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