Omap Clock Generation; Dsp Clock Domain; Clock Source - Texas Instruments OMAP5910 Reference Manual

12.2 Clock Source

Figure 102. OMAP Clock Generation
CLKREF DPLL1
Figure 103. DSP Clock Domain
DPLL1
CLKREF
SPRU890A
The OMAP clock system is organized around three main clock domains: the
MPU, DSP, and traffic controller clock domains. There is a clock generator
associated with each clock domain (see Figure 102). The input clock to the
three clock generators can be taken from two sources: the output of a digital
phase locked loop module called DPLL1, or the input clock source to the
DPLL1 module. The input clock source to DPLL1, called CLKREF, can be
generated through the use of an on-chip oscillator or supplied by an external
device.
M
CK_GEN1
u
x
M
CK_GEN2
u
x
M
CK_GEN3
u
x
The DSP clock domain output clock, CK_GEN2, is further distributed to
different modules within the DSP subsystem (Figure 103). The frequencies of
these individual clock signals can be programmed through the use of various
clock dividers within the DSP clock generator.
CK_GEN2
M
u
x
The DSP clock generator on both OMAP5910 and OMAP5912 provides two
clocks which affect most of the modules described in this reference guide: the
DSP subsystem master clock and the DSP MMU clock (see Figure 104).
DSP Subsystem Reset, Clocking, Idle Control, and Boot
MPU clock
generator
(CLKM1)
DSP clock
generator
(CLKM2)
Traffic controller
clock generator
(CLKM3)
DSP_CK
DSPMMU_CK
DSPTIM_CK
DSP clock
DSPWDT_CK
domain
(CLKM2) DSPINTH_CK
DSPPER_CK
DSPXOR_CK
To MPU clock domain
To DSP clock domain
To traffic controller clock
domain
DSP
DSP MMU
DSP private timers
DSP watchdog timer
DSP interrupt handler
DSP external
peripherals
DSP Subsystem 217