Retry Timing (Read) - Renesas NU85E Preliminary User's Manual

32-bit microprocessor core
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CHAPTER 5 BBR
Figure 5-13. Retry Timing (Read)
VPA13 to VPA0
Address
(Output)
VPDI15 to VPDI0
Data
Data
(Input)
VPWRITE (Output)
VPSTB (Output)
VPUBENZ (Output)
VPLOCK (Output)
VPRETR (Input)
VPDACT (Input)
Remark If the VPRETR and VPDACT signals are high level at the falling edge of the VPSTB signal, the
VPSTB signal becomes active, and the read operation is performed again.
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Preliminary User's Manual A14874EJ3V0UM

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