Renesas NU85E Preliminary User's Manual page 221

32-bit microprocessor core
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Figure 8-6. Servicing Example in Which Another Interrupt Request Is Issued During Interrupt Servicing (2/2)
Main routine
Interrupt request<j>
EI
Interrupt request<k>
Interrupt request<i>
(level 2)
Interrupt request<m>
Interrupt request<n>
Interrupt request<l>
(level 2)
Interrupt request<o>
Interrupt request<p>
(level 3)
Interrupt request<t>
(level 2
Interrupt request<u>
(level 2
Interrupt request<s>
(level 1)
Notes 1. Default priority is lower.
2. Default priority is higher.
CHAPTER 8 INTC
Servicing of <i>
EI
(level 3)
(level 1)
Servicing of <j>
Servicing of <l>
(level 3)
(level 1)
Servicing of <n>
Servicing of <m>
Servicing of <o>
EI
Interrupt request<q>
(level 2)
(level 1)
If levels 3 to 0 are acknowledged
Servicing of <s>
)
Note 1
)
Note 2
Servicing of <u>
Servicing of <t>
Preliminary User's Manual A14874EJ3V0UM
Servicing of <k>
Interrupt request <j> is held pending because
its priority is lower than that of <i>.
Interrupt request <k> that occurs after <j> is
acknowledged because it has the higher priority.
Interrupt requests <m> and <n> are held pending
because servicing of <l> is performed in the
interrupt disabled status.
Pending interrupt requests are acknowledged after
servicing of interrupt request <l>.
At this time, interrupt request <n> is acknowledged
first even though <m> has occurred first because the
priority of <n> is higher than that of <m>.
Servicing of <p>
Servicing of <q>
EI
EI
Interrupt request<r>
(level 0)
Pending interrupt requests <t> and <u> are
acknowledged after servicing of <s>.
Because the priorities of <t> and <u> are the same,
<u> is acknowledged first according to the default priority,
regardless of the order in which the interrupt requests
have been generated.
Servicing of <r>
EI
219

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