Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (7/12)
VBCLK (Input)
VMTTYP1, VMTTYP0 (Output)
(1,0)
VMLOCK (Output)
VMA27 to VMA0 (Output)
A.0
VMWRITE (Output)
L
VMBENZ3 to VMBENZ0 (Output)
VMCTYP2 to VMCTYP0 (Output)
VMSEQ2 to VMSEQ0 (Output)
(0,1,0)
VMSIZE1, VMSIZE0 (Output)
VMSTZ (Output)
VMBSTR (Output)
VBDC (Output)
VBDV (Output)
L
VDCSZ7 to VDCSZ0 (Output)
VDSELPZ (Output)
H
VBDI31 to VBDI0 (Input)
VBDO31 to VBDO0 (Output)
L
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
(g) 8-bit bus (4-byte sequential transfer, external ROM fetch)
Read
Idle
(1,1)
(0,0)
A.1
A.2
A.3
(1,1,1,0)
(1,1,1,1)
(0,0,0)
(0,0,1)
(0,0,0)
(1,0)
xxH
FFH
D.0
D.1
D.2
D.3
Read
(1,0)
(1,1)
A.4
A.5
A.6
A.7
(1,1,1,0)
(0,0,0)
(0,1,0)
(0,0,1)
(0,0,0)
(1,0)
xxH
D.4
D.5
D.6
Idle
(0,0)
(1,1,1,1)
FFH
D.7