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(4) CPU access during DMA transfer
The CPU can access external memory, peripheral macros, or RAM for which no DMA transfer is being
performed.
The DMAC has a higher VSB bus access right priority than the CPU, so the access from the CPU to the VSB
generated during the DMA transfer must wait until the DMA transfer is complete and the bus is available for the
CPU. However, while DMA transfer is being performed between the external memory and peripheral macro, the
CPU can access the RAM. Also, the CPU can access the external memory and peripheral macro using the VSB
when DMA transfer is being performed between RAMs that are directly connected to the VDB.
(5) DMA transfer end interrupt
The DMA transfer end interrupt is not generated when DMA transfer is complete. If the generation of an interrupt
coinciding with the completion of transfer is required, input the DMATCOn signal to the INTm pin and perform
maskable interrupt servicing (n = 3 to 0, m = 63 to 0).
(6) DMARQn signal retention
The DMARQn signal must retain the request until the DMACTVn signal becomes active.
If the DMARQn signal is made inactive before the DMACTVn signal becomes active, DMA transfer may not be
executed (n = 3 to 0).
(7) VMLOCK signal
If the destination of the DMA transfer is the RAM connected to the VDB, the VMLOCK signal will not become
active in any transfer mode (single transfer, etc.) (the VMLOCK signal becomes active only when two or more
VSB cycles are generated during 2-cycle transfer).
If the destination of the DMA transfer is the VSB, the VMLOCK signal stays active in the line transfer mode, in
either 2-cycle transfer or flyby transfer, until the fourth DMA transfer is performed. Therefore, during a DMA line
transfer in which the destination is the VSB, the VSB is locked until one line transfer is complete and the bus is
retained. During 2-cycle single transfer, single-step transfer, or block transfer, the VMLOCK signal becomes
inactive for each DMA transfer, therefore other VSB requests (VAREQ), such as SDRAM refresh, that have a
higher priority are acknowledged and the bus can be released. During block transfer, the VSB bus access right
is relinquished in the middle of transfer, and the remaining transfer is executed when the bus access right
becomes available again.
CHAPTER 7 DMAC
Preliminary User's Manual A14874EJ3V0UM
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