Renesas NU85E Preliminary User's Manual page 184

32-bit microprocessor core
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Figure 7-31 shows an example of the timing of a 2-cycle single-step transfer (between external SRAMs
connected to the NT85E500). The settings of the registers in this figure are as follows.
[Register settings]
• DBCn register = 0002H (3 transfers)
• ASC register
Note
= 0000H (No address setting wait states)
• BCC register
Note
= 0000H (No idle states)
• DWC0 register
Note
= 7377H (CS2 wait states = 3)
Note An NT85E500 register.
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CHAPTER 7 DMAC
Preliminary User's Manual A14874EJ3V0UM

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