Line Transfer Example 3; Line Transfer Example 4 - Renesas NU85E Preliminary User's Manual

Figures 7-20 and 7-21 show line transfer mode examples in which a lower priority DMA transfer request is
generated within one clock after the end of a line transfer. When two DMA transfer request signals are activated at
the same time, the two DMA transfers are performed alternately.
DMA channels 0 and 3 in Figure 7-20 are used for line transfer.
DMARQ0
(Input)
DMARQ3
(Input)
CPU DMA0 DMA0 DMA0 DMA0
Note The bus is always released.
DMA channel 0 in Figure 7-21 is used for a single transfer, and channel 3 is used for a line transfer.
DMARQ0
(Input)
DMARQ3
(Input)
CPU CPU DMA0 CPU DMA0
Note The bus is always released.
170
CHAPTER 7 DMAC
Figure 7-20. Line Transfer Example 3
Note
CPU DMA3 DMA3 DMA3 DMA3 CPU
Figure 7-21. Line Transfer Example 4
Note Note
CPU DMA3 DMA3 DMA3
Preliminary User's Manual A14874EJ3V0UM
Note Note
DMA0 DMA0 DMA0 DMA0 CPU DMA3 DMA3 DMA3
DMA channel 0
terminal count
Note Note
DMA3 CPU DMA0 CPU DMA3 DMA3
DMA3 CPU CPU
DMA channel 3
terminal count
Note
DMA3 DMA3 CPU DMA0 CPU CPU
DMA channel 0
terminal count
DMA channel 3
terminal count