Peripheral I/O Area - Renesas NU85E Preliminary User's Manual

Remark Interrupts are not acknowledged between the store instruction and the subsequent instruction for
the shaded area (refer to 8.7 Periods When Interrupts Cannot Be Acknowledged).
66
CHAPTER 3 CPU
Figure 3-11. Peripheral I/O Area
xFFFFFFH
User-usable area
xFFFA00H
xFFF9FFH
xFFF900H
xFFF8FFH
xFFF800H
xFFF7FFH
Reserved area
xFFF7C0H
xFFF7BFH
User-usable area
xFFF520H
xFFF51FH
Reserved area
xFFF500H
xFFF4FFH
Reserved area
(MEMC control register)
xFFF480H
xFFF47FH
User-usable area
xFFF200H
xFFF1FFH
xFFF100H
xFFF0FFH
Reserved area
(NU85E control register)
xFFF080H
xFFF07FH
Reserved area
(instruction/data cache control register)
xFFF070H
xFFF06FH
Reserved area
(NU85E control register)
xFFF060H
xFFF05FH
Reserved area
xFFF000H
xFFEFFFH
Preliminary User's Manual A14874EJ3V0UM
Peripheral
I/O area