Renesas NU85E Preliminary User's Manual page 198

CHAPTER 7 DMAC
Figure 7-38 shows an example of the timing of a flyby single-step transfer (from external I/O to external SRAM
connected to the NT85E500). The settings of the registers in this figure are as follows.
[Register settings]
• DBCn register = 0001H (2 transfers)
• ASC register Note
= FFEFH (CS2 address setting wait states = 2)
• BCC register
Note
= FFEFH (CS2 idle states = 2)
• DWC0 register
Note
= 7377H (CS2 wait states = 3)
Note An NT85E500 register.
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