Renesas NU85E Preliminary User's Manual page 147

(1) Clock control when setting or canceling software STOP mode
(a) When setting software STOP mode (after software STOP mode is set by setting the STP bit of the
PSC register)
<1> Set the STOP mode request signal (STPRQ) to active (high level) and output it to the memory
controller.
<2> Input the active level (high level) of the acknowledge signal (STPAK) from the memory controller that
received the STPRQ signal.
<3> Set the software STOP mode request signal (SWSTOPRQ) to active (high level) and output it to the
clock control circuit (Use this SWSTOPRQ signal to stop the VBCLK output from the clock control
circuit).
(b) When canceling software STOP mode
<1> Input a non-maskable interrupt request (NMIm), unmasked maskable interrupt request (INTn), or the
DCRESZ signal (m = 2 to 0, n = 63 to 0).
<2> Set the software STOP mode request signal (SWSTOPRQ) to inactive (low level) and output it to the
clock control circuit (clock generator starts operation).
<3> After the oscillation stabilization time, input the active level (high level) of the CGREL signal from the
clock control circuit simultaneous with the VBCLK signal (The input of the VBCLK signal returns the
STPRQ and STPAK outputs to low level).
<4> After inputting the VBCLK signal, input a high level to the DCRESZ signal.
Caution Input an active level (high level) to the CGREL pin for one clock or more.
When setting the software STOP mode again, be sure to input an inactive level (low level)
to the CGREL pin before setting.
Remark A level latch is used for the DCRESZ signal, which can therefore be input asynchronously to
VBCLK.
CHAPTER 6 STBC
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