Renesas NU85E Preliminary User's Manual page 30

Pin Name
Peripheral EVCLRIP
evaluation chip
EVINTAK
mode pins
EVINTRQ
EVINTLV6 to EVINTLV0
Operation mode IFIROME
setting pins
IFIROB2
IFIRA64
IFIRA32
IFIRA16
IFIMAEN
IFID256
IFINSZ1, IFINSZ0
IFIWRTH
IFIUNCH1
IFIUNCH0
PHEVA
IFIROBE
IFIROPR
IFIRASE
IFIRABE
IFIMODE3
IFIMODE2
IFIUSWE
FCOMB
Test mode pins TBI39 to TBI0
TBO34 to TBO0
TEST
BUNRI
BUNRIOUT
PHTDO1, PHTDO0
TESEN
VPTCLK
PHTDIN1, PHTDIN0
VPRESZ
PHTEST
TMODE1
TMODE0
TBREDZ
Note Connected internally to bus holder.
28
CHAPTER 2 PIN FUNCTIONS
I/O
Input ISPR clear input
Input Interrupt acknowledge input
Output Interrupt request output
Output Interrupt vector output
Input ROM mapping enable input
Input ROM area location setting input
Input RAM area size selection input
Input RAM area size selection input
Input RAM area size selection input
Input Misalign access setting input
Input Data area setting input
Input VSB data bus size (initial value) selection input
Input Data cache write-back/write-through mode selection input
Input Data cache setting input
Input Instruction cache setting input
Input Peripheral evaluation chip mode setting input
Input NEC reserved pins (input low level)
Input
Input
Input
Input
Input
Input
Input
Input Input test bus
Output Output test bus
Input Test bus control input
Input Normal/test mode selection input
Output Test mode status output
Note
Input Peripheral macro test input
Output Peripheral macro test enable output
Output Peripheral macro test clock output
Output Peripheral macro test output
Output Peripheral macro reset output
Output Peripheral test mode status output
Output Test mode selection output
Output NEC reserved pins (leave open)
Output
Preliminary User's Manual A14874EJ3V0UM
Function
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