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Related Manuals for Renesas SuperH HS7710KCM02HE
Summary of Contents for Renesas SuperH HS7710KCM02HE
- Page 1 REJ10B0186-0100 SuperH Family E10A Emulator Additional Document for User’s Manual Specific Guide for the SH7710 E10A Emulator Renesas Microcomputer Development Environment System SuperH Family / SH7700 Series SH7710 E10A HS7710KCM02HE Rev.1.00 Revision Date: Mar. 01, 2005...
- Page 3 (iii) prevention against any malfunction or mishap. 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
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Page 5: Table Of Contents
Section 1 Connecting the Emulator with the User System ...1 Components of the Emulator ... 1 Connecting the Emulator with the User System ... 3 Installing the H-UDI Port Connector on the User System ... 4 Pin Assignments of the H-UDI Port Connector ... 4 Recommended Circuit between the H-UDI Port Connector and the MPU... -
Page 7: Section 1 Connecting The Emulator With The User System
Section 1 Connecting the Emulator with the User System Components of the Emulator The SH7710 E10A emulator supports the SH7710. Table 1.1 lists the components of the emulator. Table 1.1 Components of the Emulator (HS7710KCM01H, HS7710KCM02H, HS7710KCI01H, or HS7710KCI02H) Classi- fication Component Hard- Card emulator... - Page 8 Table 1.1 Components of the Emulator (HS7710KCM01H, HS7710KCM02H, HS7710KCI01H, or HS7710KCI02H) (cont) Classi- fication Component Hard- Ferrite core ware (connected with the user interface cable) Soft- SH7710 E10A ware emulator setup program, SuperH Family E10A Emulator User’s Manual, and Specific Guide for the SH7710 E10A Emulator Note: The EMI is an abbreviation of the Electrical Magnetic Interference.
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Page 9: Connecting The Emulator With The User System
Connecting the Emulator with the User System To connect the E10A emulator (hereinafter referred to as the emulator), the H-UDI port connector must be installed on the user system to connect the user system interface cable. When designing the user system, refer to an example of recommended connection between the connector and the MPU shown in this manual. -
Page 10: Installing The H-Udi Port Connector On The User System
Installing the H-UDI Port Connector on the User System Table 1.3 shows the recommended H-UDI port connectors for the emulator. Table 1.3 Recommended H-UDI Port Connectors Connector Type Number 36-pin connector DX10M-36S DX10M-36SE, DX10G1M-36SE 14-pin connector 2514-6002 Note: When designing the 36-pin connector layout on the user board, do not connect any components under the H-UDI connector. - Page 11 Input/ SH7710 Signal Output Pin No. AUDCK Output AUDATA0 Output AUDATA1 Output AUDATA2 Output AUDATA3 Output /AUDSYNC Output Input Notes: 1. Input to or output from the user system. 2. The slash (/) means that the signal is active-low. 3. The emulator monitors the GND signal of the user system and detects whether or not the user system is connected.
- Page 12 Pin No. 10, 12, and 13 Notes: 1. Input to or output from the user system. Pin 1 mark Pin 8 Pin 1 Figure 1.3 Pin Assignments of the H-UDI Port Connector (14 Pins) SH7710 Input/ Pin No. Signal Output* Input /TRST Input...
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Page 13: Recommended Circuit Between The H-Udi Port Connector And The Mpu
Recommended Circuit between the H-UDI Port Connector and the 1.5.1 Recommended Circuit (36-Pin Type) Figure 1.5 shows a recommended circuit between the H-UDI port connector (36 pins) and the MPU. Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector. 2. - Page 14 Note: Schottky-barrier diode Figure 1.4 Countermeasure against the Leakage Current in the Emulator The result above differs depending on the circuit and can only be used as a reference. 7. The resistance values shown in figure 1.5 are recommended. 8. For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related device.
- Page 15 VccQ (3.3 V) H-UDI port connector (36-pin type) AUDCK AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDSYNC N.C. N.C. TRST ASEBRKAK N.C. RESET N.C. Figure 1.5 Recommended Circuit for Connection between the H-UDI Port Connector and 4.7 kΩ 4.7 kΩ Reset signal 1 kΩ MPU (36-Pin Type) VccQ (3.3 V) SH7710...
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Page 16: Recommended Circuit (14-Pin Type)
1.5.2 Recommended Circuit (14-Pin Type) Figure 1.7 shows a recommended circuit between the H-UDI port connector and the MPU. Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector. The processing of the /ASEMD0 pin differs depending on whether the emulator is used or not. - Page 17 Note: Schottky-barrier diode Figure 1.6 Countermeasure against the Leakage Current in the Emulator The result above differs depending on the circuit and can only be used as a reference. The resistance values shown in figure 1.7 are recommended. For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related device.
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Page 19: Section 2 Specifications Of The Sh7710 E10A Emulator's Software
Section 2 Specifications of the SH7710 E10A Emulator’s Differences between the SH7710 and the Emulator 1. When the emulator system is initiated, it initializes the general registers and part of the control registers as shown in table 2.1. The initial values of the actual SH7710 registers are undefined. Table 2.1 Register Initial Values at Emulator Link Up Register R0 to R14... - Page 20 3. Low-Power States (Sleep, Software Standby, and Module Standby) For low-power consumption, the SH7710 has sleep, software standby, and module standby states. The sleep, software standby, and module standby states are switched using the SLEEP instruction. When the emulator is used, only the sleep state can be cleared with either the normal clearing function or with the [STOP] button, and a break will occur.
- Page 21 8. Cache Operation during User Program Break When cache is enabled, the emulator accesses the memory by the following methods: At memory write: Writes through the cache, then writes to the memory. At memory read: Does not change the cache write mode that has been set. Therefore, when memory read or write is performed during user program break, the cache state will be changed.
- Page 22 Table 2.2 Watchdog Timer Register Register Name Usage WTCSR(W) Write WTCNT(W) Write WTCSR(R) Read WTCNT(R) Read The watchdog timer operates only when the user program is executed. Do not change the value of the frequency change register in the [IO] window or [Memory] window. The internal I/O registers can be accessed from the [IO] window.
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Page 23: Specific Functions For The Sh7710 E10A Emulator
Specific Functions for the SH7710 E10A Emulator 2.2.1 Emulator Driver Selection Table 2.3 shows drivers which are selected in the [E10A Driver Details] dialog box. Table 2.3 Type Number and Driver Type Number HS7710KCM01H HS7710KCM02H HS7710KCI01H HS7710KCI02H Driver E10A PC Card Driver 3 E10A PC Card Driver 4 E10A PCI Card Driver 3 E10A PCI Card Driver 4... -
Page 24: Break Condition Functions
2.2.2 Break Condition Functions In addition to BREAKPOINT functions, the emulator has Break Condition functions. Three types of conditions can be set under Break Condition 1, 2, 3. Table 2.4 lists these conditions of Break Condition. Table 2.4 Types of Break Conditions Break Condition Type Address bus condition (Address) Data bus condition (Data) -
Page 25: Trace Functions
Table 2.5 lists the combinations of conditions that can be set under Break Condition 1, 2, 3. Table 2.5 Dialog Boxes for Setting Break Conditions Type Address Condition Dialog Box (Address) [Break Condition 1] dialog box [Break Condition 2] dialog box [Break Condition 3] dialog box Notes: 1. - Page 26 AUD Trace Functions: This function is operational when the AUD pin of the device is connected to the emulator. Table 2.8 shows the AUD trace acquisition mode that can be set in each trace function. Table 2.8 AUD Trace Acquisition Mode Type Mode Continuous...
- Page 27 To set the AUD trace acquisition mode, click the [Trace] window with the right mouse button and select [Setting] from the pop-up menu to display the [Acquisition] dialog box. The AUD trace acquisition mode can be set in the [AUD mode1] or [AUD mode2] group box in the [Trace mode] page of the [Acquisition] dialog box.
- Page 28 (a) Branch Trace Function The branch source and destination addresses and their source lines are displayed. Branch trace can be acquired by selecting the [Branch trace] check box in the [AUD function] group box of the [Trace mode] page. The branch type can be selected in the [AUD Branch trace] page. Figure 2.2 [AUD Branch trace] Page (b) Window Trace Function Memory access in the specified range can be acquired by trace.
- Page 29 Notes: 1. When the [L-bus] or [I-bus] radio button is selected, the following bus cycles will be traced. L-bus: A bus cycle generated by the CPU is acquired. A bus cycle is also acquired when the cache has been hit. I-bus: A bus cycle generated by the CPU or DMA is acquired.
- Page 30 (c) Software Trace Function Note: This function can be supported with SHC/C++ compiler (manufactured by Renesas Technology Corp.; including OEM and bundle products) V7.0 or later. When a specific instruction is executed, the PC value at execution and the contents of one general register are acquired by trace.
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Page 31: Notes On Using The Jtag Clock (Tck) And Aud Clock (Audck)
9. For the AUD non-realtime trace, the written access may be executed again. If this is a problem on the user system, do not use the non-realtime trace. Internal Trace Function: This function is activated by selecting the [Internal trace] radio button in the [Trace type] group box of the [Trace mode] page. - Page 32 An area that can be only read by MMU 3. During step operation, a BREAKPOINT is disabled. 4. Conditions set at Break Condition 2 are disabled when an instruction to which a BREAKPOINT has been set is executed. Do not set a BREAKPOINT to an instruction in which Break Condition 2 is satisfied.
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Page 33: Notes On Setting The [Break Condition] Dialog Box And The Breakcondition_ Set Command
value after setting. When no ASID value is specified, the BREAKPOINT is set to a virtual address corresponding to the ASID value at command input. 12. An address (physical address) to which a BREAKPOINT is set is determined when the BREAKPOINT is set. -
Page 34: Note On Setting The Ubc_Mode Command
2.2.7 Note on Setting the UBC_MODE Command In the [Configuration] dialog box, if [User] is set while the [UBC mode] list box has been set, the STEP-type commands that use Break Condition 2 for implementation cannot be used. 2.2.8 Performance Measurement Function The SH7710 E10A emulator supports the performance measurement function. - Page 35 Figure 2.4 [Performance Analysis] Dialog Box (b) Measurement range One of the following ranges can be specified. This depends on the item selected for [Mode] in the [Performance Analysis] dialog box. 1. From the start to the end of the user program execution (When Normal Break is selected for [Mode]) 2.
- Page 36 Notes: 1. When the second and third ranges are specified, execute the user program after the measurement start condition is set to Break Condition 1 (or Break Condition 2) and the measurement end condition to Break Condition 2 (or Break Condition 1). Step operation is not possible when Break condition 1->2 or Break condition 2->1 is selected for the PERFORMANCE_SET command or in [Mode] of the [Performance Analysis] dialog box.
- Page 37 Table 2.10 Measurement Item Selected Name Disabled Elapsed time Number of execution states Branch instruction counts Number of execution instructions DSP-instruction execution counts Instruction/data conflict cycle Other conflict cycles than instruction/data Exception/interrupt counts Data-TLB miss cycle Instruction-TLB miss cycle Interrupt counts Number of BL=1 instructions Number of MD=1 instructions Instruction cache-miss counts...
- Page 38 Table 2.10 Measurement Item (cont) Selected Name Non-cacheable area data access cycle Cacheable area access cycle Cacheable area instruction access cycle Cacheable area data access cycle Access counts other than instruction/data Non-cacheable area access counts Non-cacheable area instruction access counts Non-cacheable area data access counts Cacheable area access counts Cacheable area instruction access counts...
- Page 39 Note: If a performance counter overflows as a result of measurement, “********” will be displayed. 3. Initializing the measured result To initialize the measured result, select [Initialize] from the popup menu in the [Performance Analysis] window or specify INIT with the PERFORMANCE_ANALYSIS command.
- Page 41 Specific Guide for the SH7710 E10A Emulator Publication Date: Rev.1.00, March 1, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
- Page 42 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
- Page 43 SuperH Family E10A Emulator Additional Document for User’s Manual Specific Guide for the SH7710 E10A Emulator...