Cache Configuration; Cache Configuration Register (Bhc) - Renesas NU85E Preliminary User's Manual

4.7 Cache Configuration

The cache configuration register (BHC) is used to set the cache memory configuration for each CSn area selected
by the chip select signals (VDCSZn) (see Figures 4-3 and 4-4) (n = 7 to 0).
The BHC register can be read or written in 16-bit units.
Cautions 1. Be sure to disable the cache for big endian format CSn area or CSn areas set as the following
areas (n = 7 to 0).
• • • • ROM area
• • • • RAM area
• • • • Peripheral I/O area
• • • • Programmable peripheral I/O area
2. The instruction/data cache enabled setting (BHn0/BHn1 bit = 1 (set)) is only valid when a low
level is being input (cache enabled) to the IFIUNCH0 or IFIUNCH1 pin. In other cases, the
instruction/data cache enabled setting is invalid even if the BHn0/BHn1 bit is set to 1.
3. When using the data cache, set this register after setting the data cache's data cache control
register (DCC).
15 14 13
BH BH BH BH
BHC
71 70 61
Bit position Bit name
15, 13, 11, BHn1
9, 7, 5, 3, 1
14, 12, 10, BHn0
8, 6, 4, 2, 0
Remark n = 7 to 0
90
CHAPTER 4 BCU
Figure 4-11. Cache Configuration Register (BHC)
12 11 10 9 8 7
BH BH BH BH BH
60 51 50 41 40 31
Sets whether or not the data cache located in the CSn area can be used.
BHn1
0 Cache disabled
1 Cache enabled
Sets whether or not the instruction cache located in the CSn area can be used.
BHn0
0 Cache disabled
1 Cache enabled
Preliminary User's Manual A14874EJ3V0UM
6 5 4 3 2 1
BH BH BH BH BH BH
30 21 20 11 10 01
Function
Data cache setting
Instruction cache setting
0
BH Address After reset
00 FFFFF06AH 0000H