Single Transfer Example 3; Single Transfer Example 4 - Renesas NU85E Preliminary User's Manual

Figure 7-14 shows a single transfer mode example in which a lower priority DMA transfer request is generated
within one clock after the end of a single transfer. DMA channels 0, 3 are used for a single transfer. When two DMA
transfer request signals are activated at the same time, the two DMA transfers are performed alternately.
DMARQ0
(Input)
DMARQ3
(Input)
CPU CPU DMA0 CPU DMA0
Note The bus is always released.
Figure 7-15 shows a single transfer mode example in which two or more lower priority DMA transfer requests are
generated within one clock after the end of a single transfer. DMA channels 0, 2, and 3 are used for a single transfer.
When three or more DMA transfer request signals are activated at the same time, always the two highest priority
DMA transfers are performed alternately.
DMARQ0
(Input)
DMARQ2
(Input)
DMARQ3
(Input)
Note
CPU DMA3 CPU DMA3 CPU
Note The bus is always released.
CHAPTER 7 DMAC
Figure 7-14. Single Transfer Example 3
Note Note Note
CPU DMA3 CPU DMA0
Figure 7-15. Single Transfer Example 4
Note Note Note
DMA2 CPU DMA0 CPU DMA2 CPU
Preliminary User's Manual A14874EJ3V0UM
Note Note Note
CPU DMA3 CPU DMA0 CPU
DMA channel 3
terminal count
Note Note Note Note
DMA0 CPU DMA2 CPU DMA3 CPU DMA2 CPU
DMA channel 0
terminal count
Note
DMA0 CPU DMA0 CPU CPU
DMA channel 0
terminal count
Note
DMA3 CPU CPU
DMA channel 3
terminal count
DMA channel 2
terminal count
167