Programmable Peripheral I/O Area Selection Function - Renesas NU85E Preliminary User's Manual

Figure 4-4. CSC0 and CSC1 Register Setting Example (256 MB Mode) (2/2)
Remark The values within parentheses indicate the size of each bank (unit: bytes).
The values within brackets indicate the corresponding VDCSZn signal (n = 7 to 0).

4.4 Programmable Peripheral I/O Area Selection Function

The NU85E has a 4 KB peripheral I/O area that is allocated in advance in the address space and a 12 KB
programmable peripheral I/O area that can be allocated at arbitrary addresses according to register settings.
Registers for peripheral macros connected to the NPB or user logic can be freely located in the programmable
peripheral I/O area.
Caution Be sure to allocate the programmable peripheral I/O area to a CSn area in which both little endian
and instruction/data cache-prohibited settings have been made (n = 7 to 0).
CHAPTER 4 BCU
(c) Memory map
Bank 15 (2M) [VDCSZ5]
Bank 14 (2M) [VDCSZ7]
Bank 13 (2M) [VDCSZ7]
Area 3 (Bank 12 (2M))
[VDCSZ6]
[VDCSZ4]
Area 2
Area 1 [VDCSZ3]
[VDCSZ1]
Area 0 Bank 3 (2M) [VDCSZ2]
Bank 2 (2M) [VDCSZ2]
Bank 1 (2M) [VDCSZ0]
Bank 0 (2M) [VDCSZ0]
Preliminary User's Manual A14874EJ3V0UM
CS5 area
CS7 area
CS6 area
CS4 area
CS3 area
CS1 area
CS2 area
CS0 area
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