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Pin Name
VSB pins
VSLOCK
VSWAIT
VSLAST
VSAHLD
VSSELPZ
VBDC
VBDV
VDCSZ7 to VDCSZ0
System control
DCRESZ
pins
VBCLK
CGREL
SWSTOPRQ
HWSTOPRQ
DCSTOPZ
STPRQ
STPAK
DMAC pins
IDMASTP
DMARQ3 to DMARQ0
DMTCO3 to DMTCO0
DMACTV3 to DMACTV0
INTC pins
DCNMI2 to DCNMI0
INT63 to INT0
VFB pins
IROMA19 to IROMA2
IROMZ31 to IROMZ0
IROMEN
IROMWT
IROMCS
IROMIA
IROMAE
VDB pins
IRAMA27 to IRAMA2
IRAMZ31 to IRAMZ0
IRAOZ31 to IRAOZ0
IRAMEN
IRAMWR3 to IRAMWR0
IRAMRWB
IRAMWT
Instruction
IBDRRQ
cache pins
IBEA25 to IBEA2
IBAACK
26
CHAPTER 2 PIN FUNCTIONS
I/O
Input
Bus lock input
Output
Wait response output
Output
Last response output
Output
Address hold response output
Input
Peripheral I/O area access status input
Output
Data input (VBDI31 to VBDI0) control output
Output
Data output (VBDO31 to VBDO0) control output
Output
Chip select output
Input
System reset input
Input
Internal system clock input
Input
Clock generator release input
Output
Software STOP mode request output to clock generator
Output
Hardware STOP mode request output to clock generator
Input
Hardware STOP mode request input
Output
Hardware/software STOP mode request output to MEMC
Input
Acknowledge input for STPRQ input of MEMC
Input
DMA transfer termination input
Input
DMA transfer request input
Output
Terminal count (DMA transfer completion) output
Output
DMA acknowledge output
Input
Non-maskable interrupt request (NMI) input
Input
Maskable interrupt request input
Output
ROM address output
Input
ROM data input
Output
ROM access enable output
Input
ROM wait input
Output
NEC reserved pins (leave open)
Output
Output
Output
RAM address output
Input
RAM data input
Output
RAM data output
Output
RAM access enable output
Output
RAM write enable output
Output
RAM read/write status output
Input
RAM wait input
Input
Fetch request input from instruction cache
Input
Fetch address input from instruction cache
Output
Address acknowledge output to instruction cache
Preliminary User's Manual A14874EJ3V0UM
Function
(2/4)
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