Read/Write Timing Of Bus Slave Connected To Npb - Renesas NU85E Preliminary User's Manual

32-bit microprocessor core
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Figure 5-14. Read/Write Timing of Bus Slave Connected to NPB (1/4)
(a) Example of timing of word-data write to NPB peripheral macro (programmable peripheral I/O area)
VBCLK (Input)
VMTTYP1, VMTTYP0 (Output)
(1,0)
VMLOCK (Output)
VMA27 to VMA0 (Output)
VMWRITE (Output)
VMBENZ3 to VMBENZ0 (Output)
VMCTYP2 to VMCTYP0 (Output)
VMSEQ2 to VMSEQ0 (Output)
VMSIZE1, VMSIZE0 (Output)
VMSTZ (Output)
VDCSZ7 to VDCSZ0 (Output)
VDSELPZ (Output)
VBDI31 to VBDI0 (Input)
L
VBDO31 to VBDO0 (Output)
VSWAIT (Output)
VSAHLD (Output)
VSLAST (Output)
VMWAIT (Input)
VMAHLD (Input)
L
VMLAST (Input)
VPA13 to VPA0 (Output)
VPDI15 to VPDI0 (Input)
VPDO15 to VPDO0 (Output)
VPSTB (Output)
VPRETR (Input)
L
VPWRITE (Output)
VPUBENZ (Output)
L
(1,1)
(1,0)
2403800H
(1,1,0,0)
(0,0,1)
(0,0,1)
(1,0)
FFH
xxxx5678H
3800H
5678H
(1,1)
2403802H
(0,0,0)
xxxx1234H
3802H
1234H

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