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1.5.2 Internal units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
and logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a hardware multiplier that enables high-speed processing of 32-bit ×
32-bit multiplication and a barrel shifter, help accelerate the processing of complex instructions.
In addition, the CPU has an on-chip RCU interface for connecting to the RCU (See CHAPTER 3 CPU).
(2) BCU
The bus control unit (BCU), which operates as a bus master on the VSB, controls the on-chip bus bridge (BBR),
test interface control unit (TIC), and peripheral macros (bus slaves) such as the memory controller (MEMC)
connected to the VSB (See CHAPTER 4 BCU).
(3) BBR
The bus bridge (BBR) converts signals for the VSB to signals for the NPB.
The BBR sets up the wait insertion function and retry function for peripheral macros connected to the NPB (See
CHAPTER 5 BBR).
(4) STBC
The standby control unit (STBC) controls the external clock generator (CG) when the power save function (HALT
mode, software STOP mode, or hardware STOP mode) is executed (See CHAPTER 6 STBC).
(5) DMAC
The DMA control unit (DMAC) is a four-channel control unit that controls data transfers between memory and
peripheral macros or between memory and memory based on DMA transfer requests issued by means of the
DMARQ3 to DMARQ0 pins or software triggers (See CHAPTER 7 DMAC).
(6) INTC
The interrupt control unit (INTC) processes various types of interrupt requests (See CHAPTER 8 INTC).
(7) TIC
The test interface control unit (TIC) is used for test function control. When the TIC is set to test mode, test
control signals become effective (See CHAPTER 9 TEST FUNCTION).
(8) Bus arbiter
The bus arbiter receives bus control requests from multiple bus masters and arbitrates bus access rights.
CHAPTER 1 INTRODUCTION
Preliminary User's Manual A14874EJ3V0UM
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