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(4) IFIMAEN (input)
This is the misalign access setting input pin.
Misalign access is enabled or disabled as follows according to the input level to this pin.
• Low level: Misalign access disabled
• High level: Misalign access enabled
(5) IFID256 (input)
This is the data area setting input pin. It is used to set the data area size.
Each mode is set as follows according to the input level to this pin.
For details, see 3.3.2 Data area.
• Low level: 64 MB mode
• High level: 256 MB mode
(6) IFINSZ1, IFINSZ0 (input)
These are the VSB data bus size (initial value) selection input pins.
The VSB data bus size is set as follows according to the input level to these pins.
IFINSZ1
0
0
1
1
Remark
0: low-level input 1: high-level input
If the VSB data bus size is changed after reset through the bus size configuration register (BSC), the setting of
the BSC register is valid regardless of the input level to these pins.
(7) IFIWRTH (input)
This is the data cache write-back or write-through mode selection input pin.
When using the data cache, connect to the IFIWRTH pin of the data cache.
Each mode is set as follows according to the input level to this pin.
• Low level: Write-back mode
• High level: Write-through mode
(8) IFIUNCH1 (input)
This is the data cache setting input pin.
When using the data cache, connect to the IFIUNCH1 pin of the data cache.
The data cache is enabled or disabled as follows according to the input level to this pin.
• Low level: Data cache is enabled
• High level: Data cache is disabled
CHAPTER 2 PIN FUNCTIONS
Table 2-9. IFINSZ1 and IFINSZ0 Signals
IFINSZ0
0
32 bits
1
16 bits
0
8 bits
1
Setting prohibited
Preliminary User's Manual A14874EJ3V0UM
VSB Data Bus Size
43
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