Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (8/12)
VBCLK (Input)
VMTTYP1, VMTTYP0 (Output)
VMLOCK (Output)
L
VMA27 to VMA0 (Output)
A.0
A.1
VMWRITE (Output)
VMBENZ3 to VMBENZ0 (Output)
(0,0,0,0) (1,1,0,0)
VMCTYP2 to VMCTYP0 (Output)
VMSEQ2 to VMSEQ0 (Output)
VMSIZE1, VMSIZE0 (Output)
(1,0)
(0,1)
VMSTZ (Output)
VMBSTR (Output)
L
VBDC (Output)
VBDV (Output)
VDCSZ7 to VDCSZ0 (Output)
VDSELPZ (Output) H
VBDI31 to VBDI0 (Input)
D.0
VBDO31 to VBDO0 (Output)
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
Word transfer
Halfword transfer
(h) 32-bit bus (little-endian, word/halfword/byte transfer)
Read
(1,0)
A.2
A.3
A.4
A.5
A.6
(0,0,1,1) (1,1,1,0) (1,1,0,1) (1,0,1,1) (0,1,1,1)
(0,0,1)
(0,0,0)
(0,0)
xxH
D.1
D.2
D.3
D.4
D.5
D.6
Byte transfer
Idle
Write
(0,0)
(1,0)
A.7
A.8
A.9
A.10
(1,1,1,1)
(0,0,0,0) (1,1,0,0)
(0,0,1,1) (1,1,1,0) (1,1,0,1) (1,0,1,1) (0,1,1,1)
(0,0,1)
(0,0,0)
(1,0)
(0,1)
FFH
xxH
D.7
D.8
D.9
D.10
Word transfer
Halfword transfer
Idle
(0,0)
A.11
A.12
A.13
(1,1,1,1)
(0,0)
FFH
D.11
D.12
D.13
Byte transfer