Chip Area Select Control Register 1 (Csc1) - Renesas NU85E Preliminary User's Manual

15 14 13
CS CS CS CS
CSC1
43 42 41
Bit position Bit name
15 to 0 CSn3 to
CSn0
Remark n = 4 to 7
78
CHAPTER 4 BCU
Figure 4-2. Chip Area Select Control Register 1 (CSC1)
12 11 10 9 8 7
CS CS CS CS CS
40 53 52 51 50 63
When each bit is set (1), the VDCSZn signal becomes active if the condition within
parentheses holds.
Bit name
64 MB mode
CS40 VDCSZ4 (when accessing bank 12,
13, 14, or 15)
CS41 VDCSZ4 (when accessing bank 10 or
11)
CS42 VDCSZ4 (when accessing bank 9)
CS43 VDCSZ4 (when accessing bank 8)
CS50 VDCSZ5 (when accessing bank 15)
CS51 VDCSZ5 (when accessing bank 14)
CS52 VDCSZ5 (when accessing bank 13)
CS53 VDCSZ5 (when accessing bank 12)
CS60 VDCSZ6 (when accessing bank 14 or
15)
CS61 VDCSZ6 (when accessing bank 12 or
13)
CS62 VDCSZ6 (when accessing bank 11)
CS63 VDCSZ6 (when accessing bank 10)
CS70 VDCSZ7 (when accessing bank 15)
CS71 VDCSZ7 (when accessing bank 14)
CS72 VDCSZ7 (when accessing bank 13)
CS73 VDCSZ7 (when accessing bank 12)
Preliminary User's Manual A14874EJ3V0UM
6 5 4 3 2 1
CS CS CS CS CS CS
62 61 60 73 72 71
Function
VDCSZn signal that becomes active
VDCSZ4 (when accessing area 2)
(Same when each bit is cleared (0))
VDCSZ6 (when accessing area 3)
(Same when each bit is cleared (0))
0
CS Address After reset
70 FFFFF062H 2C11H
256 MB mode