Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 Preliminary User’s Manual NU85E 32-Bit Microprocessor Core Hardware NU85E NU85EA Document No. A14874EJ3V0UM00 (3rd edition) Date Published March 2002 N CP(N) Printed in Japan...
Page 4 [MEMO] Preliminary User’s Manual A14874EJ3V0UM...
Page 5 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 6 The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country.
Page 7 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
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Page 9 PREFACE Target Readers This manual is intended for users who wish to understand the hardware functions of the NU85E and NU85EA, which are the CPU cores of a cell-based IC (CBIC), to design application systems using the NU85E or NU85EA.
Page 10 • V850E1 Architecture User’s Manual (U14559E) • Memory Controller NU85E, NU85ET User’s Manual (A15019E) • Instruction Cache, Data Cache NU85E, NU85ET User’s Manual (A15241E) • CB-10 Family VX Type NU85E, NU85ET Design Manual (A15401E) • CB-10 Family VX Type Core Library CPU Core, Peripheral Design Manual (A15133E) The related documents listed above are subject to change without notice.
Page 11: Table Of Contents
Function Blocks............................22 1.5.1 Internal block diagram ........................22 1.5.2 Internal units ..........................23 Functional Differences Between NU85E and NB85E................24 CHAPTER 2 PIN FUNCTIONS ........................25 List of Pin Functions ..........................25 Explanation of Pin Functions ........................29 2.2.1 NPB pins ............................29 2.2.2...
Page 12 3.5.2 Memory controller (MEMC) control registers .................71 3.5.3 Instruction cache control registers ....................72 3.5.4 Data cache control registers ......................72 RCU Interface .............................73 3.6.1 Outline............................73 3.6.2 On-chip debugging.........................73 CHAPTER 4 BCU............................74 Features ..............................74 Memory Banks ............................74 Programmable Chip Select Function .......................77 Programmable Peripheral I/O Area Selection Function .................83 Bus Size Setting Function.........................86 Endian Setting Function..........................87...
Page 13 DMA Channel Priorities ........................... 151 Control Registers............................. 152 7.5.1 DMA source address registers 0 to 3 (DSA0 to DSA3) ...............152 7.5.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) ............154 7.5.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)..............156 7.5.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) .............157 7.5.5...
Page 14 10.5 N-Wire Type IE Connection ........................244 10.5.1 IE connector (target system side) ....................244 10.5.2 Example of recommended circuit when connecting NB85E901 and NU85E .......246 APPENDIX A ROM/RAM ACCESS TIMING.....................247 APPENDIX B INDEX ..........................249 APPENDIX C REVISION HISTORY......................254 Preliminary User’s Manual A14874EJ3V0UM...
Page 15 RAM Area ................................64 3-11 Peripheral I/O Area............................66 3-12 Connection of NU85E and N-Wire Type In-Circuit Emulator via RCU...............73 Chip Area Select Control Register 0 (CSC0).....................77 Chip Area Select Control Register 1 (CSC1).....................78 CSC0 and CSC1 Register Setting Example (64 MB Mode) ................79 CSC0 and CSC1 Register Setting Example (256 MB Mode) ................82...
Page 16 Power Save Function State Transition Diagram ....................136 Power Save Control Register (PSC)........................137 Command Register (PRCMD) .........................139 Connection of NU85E and Clock Control Circuit .....................144 Software STOP Mode Set/Cancel Timing Example..................146 Hardware STOP Mode Set/Cancel Timing Example ..................148 DMA Source Address Registers 0H to 3H (DSA0H to DSA3H)...............152 DMA Source Address Registers 0L to 3L (DSA0L to DSA3L) .................153...
Page 17 NB85E901 and NU85E Connection Example....................243 10-2 N-Wire Type IE Connection..........................244 10-3 IE Connector Pin Layout Diagram (Target System Side) ................244 10-4 Example of Recommended Circuit for IE Connection (NU85E + NB85E901) ..........246 ROM Access Timing............................247 RAM Access Timing ............................248 Preliminary User’s Manual A14874EJ3V0UM...
Page 18 LIST OF TABLES Table No. Title Page VMTTYP1 and VMTTYP0 Signals ........................30 VMBENZ3 to VMBENZ0 and VSBENZ1 Signals ....................31 VMSIZE1 and VMSIZE0 Signals ........................31 VMCTYP2 to VMCTYP0 Signals ........................32 VMSEQ2 to VMSEQ0 Signals ...........................32 IRAMWR3 to IRAMWR0 Signals ........................37 IDDRRQ, IDDWRQ, IDSEQ4, and IDSEQ2 Signals ..................39 IFIRA64, IFIRA32, and IFIRA16 Signals......................42 IFINSZ1 and IFINSZ0 Signals ...........................43 2-10...
Page 19: Chapter 1 Introduction
2 types of external bus interfaces for connection to high- and low-speed peripheral I/Os, as well as functions to interface with ROM, RAM, an instruction cache, and a data cache. This product, the “NU85E”, is a CPU core that has, among other on-chip features, a DMA controller and an interrupt controller.
Page 20: Application System Example
Remark VFB: Dedicated bus for ROM direct coupling (V850E fetch bus) VDB: Dedicated bus for RAM direct coupling (V850E data bus) Caution In this manual, representations related to the memory connected to the NU85E are unified as follows. • • • • RAM: NU85E direct-coupled RAM (connected to VDB) •...
Page 21: Features
CHAPTER 1 INTRODUCTION 1.3 Features • Number of instructions 83 • General-purpose registers 32 bits × 32 registers • Instruction set Upwardly compatible with V850 CPU Signed multiplication (32 bits × 32 bits → 64 bits) Saturated calculation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock Bit manipulation instructions Load/store instructions with long/short format...
Page 22 CHAPTER 1 INTRODUCTION • Power save function HALT mode Software STOP mode Hardware STOP mode • RCU Note interface function Note The Run Control Unit (RCU) communicates using JTAG and executes debug processing. Preliminary User’s Manual A14874EJ3V0UM...
Page 23: Symbol Diagram
CHAPTER 1 INTRODUCTION 1.4 Symbol Diagram DBI (5:0) IBDRRQ DBO (14:0) IBEA (25:2) in/out DBB (15:0) IBAACK IFIROME IBDRDY IFIROB2 IBDLE (3:0) IFIMODE2 IBEDI (31:0) IFIRA16 IBBTFT IFIRA32 IIDRRQ IFIRA64 IIEA (25:2) IFIMAEN IIAACK IFID256 IIDLEF IFINSZ (1:0) IIEDI (31:0) IFIWRTH IIBTFT IFIUNCH (1:0)
Page 24: Function Blocks
CHAPTER 1 INTRODUCTION 1.5 Function Blocks 1.5.1 Internal block diagram IBDRRQ DBI5 to DBI0 IBEA25 to IBEA2 DBO14 to DBO0 IBAACK DBB15 to DBB0 RCU interface IBDRDY IFIROME IBDLE3 to IBDLE0 IFIROB2 IBEDI31 to IBEDI0 IFIMODE2 IBBTFT IFIRA16 Instruction cache interface IIDRRQ IFIRA32 IIEA25 to IIEA2...
Page 25: Internal Units
CHAPTER 1 INTRODUCTION 1.5.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic and logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a hardware multiplier that enables high-speed processing of 32-bit × 32-bit multiplication and a barrel shifter, help accelerate the processing of complex instructions.
Page 26: Functional Differences Between Nu85E And Nb85E
CHAPTER 1 INTRODUCTION 1.6 Functional Differences Between NU85E and NB85E Item NU85E NB85E VSB data bus (n = 31 to 0) VBDIn (input), VBDOn (output) VBDn (input/output) VSB master/slave control pins VMA27 to VMA0 (output) VBA27 to VBA0 (input/output) VSA13 to VSA0 (input)
Page 27: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions (1/4) Pin Name Function NPB pins VPA13 to VPA0 Output Address output for peripheral macro connected to NPB Note VPDI15 to VPDI0 Input Data input from peripheral macro connected to NPB VPDO15 to VPDO0 Output Data output to peripheral macro connected to NPB...
Page 28 CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name Function VSB pins VSLOCK Input Bus lock input VSWAIT Output Wait response output VSLAST Output Last response output VSAHLD Output Address hold response output VSSELPZ Input Peripheral I/O area access status input VBDC Output Data input (VBDI31 to VBDI0) control output VBDV...
Page 29 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name Function Instruction IBDRDY Output Data ready output to instruction cache cache pins IBDLE3 to IBDLE0 Output Data latch enable output to instruction cache IBEDI31 to IBEDI0 Output Data output to instruction cache IIDRRQ Output Fetch request output to instruction cache IIEA25 to IIEA2...
Page 30 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name Function Peripheral EVCLRIP Input ISPR clear input evaluation chip EVINTAK Input Interrupt acknowledge input mode pins EVINTRQ Output Interrupt request output EVINTLV6 to EVINTLV0 Output Interrupt vector output Operation mode IFIROME Input ROM mapping enable input setting pins IFIROB2 Input...
Page 31: Explanation Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Explanation of Pin Functions 2.2.1 NPB pins (1) VPA13 to VPA0 (output) These are pins from which addresses are output to peripheral macros connected to the NPB. They specify the lower 14 bits. (2) VPDI15 to VPDI0 (input) These are pins to which data is input from peripheral macros connected to the NPB.
Page 32: Vsb Pins
(8) VMSTZ (output), VSSTZ (input) These are low-level active pins that indicate transfer start. The NU85E uses the VMSTZ pin when it has the bus access right, and the VSSTZ pin when it operates as a bus slave. Preliminary User’s Manual A14874EJ3V0UM...
Page 33 These pins are used to retain the bus access right. These pins are used to prohibit interruption through access from another bus master between the current transfer and the next transfer. The NU85E uses the VMLOCK pin when it has the bus access right, and the VSLOCK pin when it operates as a bus slave.
Page 34 CHAPTER 2 PIN FUNCTIONS (13) VMCTYP2 to VMCTYP0 (output) These are pins that output the current bus cycle status when the NU85E has the bus access right. Table 2-4. VMCTYP2 to VMCTYP0 Signals VMCTYP2 VMCTYP1 VMCTYP0 Bus Cycle Status Opcode fetch...
Page 35 When these signals become high level, the bus cycle changes to the wait status. The NU85E uses the VMWAIT pin when it has the bus access right, and the VSWAIT pin when it operates as a bus slave.
Page 36: System Control Pins
CHAPTER 2 PIN FUNCTIONS (20) VBDC (output) This is data input (VBDI31 to VBDI0) control signal output pin. This pin outputs a high level during a read cycle and during DMA flyby transfer from the external memory to the I/O. When connecting a bus slave that has an I/O separated data bus and a bidirectional data bus, this pin is connected to the enable pin of the 3-state buffer connected to the data bus for data input control.
Page 37: Stopping Vbclk Oscillation By System Reset
VBCLK input from the CG is stopped by using this signal. When hardware STOP mode is canceled, this pin outputs a low-level signal. (6) DCSTOPZ (input) This is a hardware STOP mode request input pin. When a low-level signal is input, the NU85E is set to hardware STOP mode. (7) STPRQ (output) This is the pin from which hardware/software STOP mode requests are output to the memory controller (MEMC).
Page 38: Dmac Pins
CHAPTER 2 PIN FUNCTIONS 2.2.4 DMAC pins (1) IDMASTP (input) This is the DMA transfer forcible interrupt input pin. Input an active level (high level) of two clocks in synchronization with the rising edge of the VBCLK signal. To restart transfer, set (1) the EN bit of the DRST register after inputting a low level to this pin. (2) DMARQ3 to DMARQ0 (input) These are the DMA transfer request input pins.
Page 39: Vdb Pins
CHAPTER 2 PIN FUNCTIONS 2.2.7 VDB pins (1) IRAMA27 to IRAMA2 (output) These pins constitute a bus from which addresses are output to RAM. The IRAMA27 to IRAMA16 signals are output for the data cache. Therefore, they do not have to be decoded when RAM is connected. (2) IRAMZ31 to IRAMZ0 (input) These pins constitute a bus to which data is input from RAM.
Page 40: Instruction Cache Pins
This is the pin from which data ready signals are output to the instruction cache. Upon an instruction cache miss-hit, when the NU85E has finished fetching the data to be read from the external memory, this signal is output to indicate that a refill for the instruction cache is ready.
Page 41: Data Cache Pins
(2) IDAACK (output) This is the pin from which acknowledgements are output to the data cache. This signal is output when the NU85E recognizes the IDEA27 to IDEA0 signals input from the data cache. (3) IDDRRQ, IDDWRQ, IDSEQ4, IDSEQ2 (input) These are the pins to which the operation type settings are input from the data cache.
Page 42 This is the pin from which read data ready signals are output to the data cache. Upon a data cache miss-hit, when the NU85E has finished fetching the data to be read from the external memory, this signal is output to indicate that a refill for the data cache is ready.
Page 43: Rcu Pins
2.2.11 Peripheral evaluation chip mode pins If a high-level signal is input to the PHEVA pin, the NU85E is set to peripheral evaluation chip mode. In peripheral evaluation chip mode, the ASIC in which the NU85E is incorporated is used as a peripheral emulation chip when the in-circuit emulator is used to perform debugging.
Page 44: Operation Mode Setting Pins
2.2.12 Operation mode setting pins The following pins are used to specify the operation mode of the NU85E. The input level to these pins should remain fixed during NU85E operation. Do not change the input level to these pins during operation.
Page 45 CHAPTER 2 PIN FUNCTIONS (4) IFIMAEN (input) This is the misalign access setting input pin. Misalign access is enabled or disabled as follows according to the input level to this pin. • Low level: Misalign access disabled • High level: Misalign access enabled (5) IFID256 (input) This is the data area setting input pin.
Page 46: Test Mode Pins
This is the peripheral evaluation chip mode setting input pin. A high level is input when the ASIC in which the NU85E has been incorporated is used as a peripheral evaluation chip. (11) IFIROBE, IFIROPR, IFIRASE, IFIRABE, IFIMODE3, IFIMODE2, IFIUSWE, FCOMB (input) These are NEC reserved pins.
Page 47 CHAPTER 2 PIN FUNCTIONS (10) VPRESZ (output) This is the pin from which reset signals are output to the peripheral macros. Caution The VPRESZ signal is the reset signal for the peripheral macros in normal operation mode as well as test mode. (11) PHTEST (output) This is the pin from which signals indicating the peripheral test mode status are output.
Page 48: Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Recommended Connection of Unused Pins (1/2) Pin Name Recommended Connection Method NPB pins VPA13 to VPA0, VPDO15 to VPDO0, Output Leave open. VPWRITE, VPSTB, VPLOCK, VPUBENZ, VPDV Note Note VPDI15 to VPDI0 , VPRETR Input Input low level.
Page 49 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Recommended Connection Method RCU pins DBI5, DBI1 Input Input high level. DBI4 to DBI2, DBI0 Input Input low level. DBO14 to DBO0 Output Leave open. DBB15 to DBB0 Leave open. Peripheral EVASTB, EVDSTB, EVIREL, EVCLRIP, Input Input low level.
Page 50: Pin Status
CHAPTER 2 PIN FUNCTIONS 2.4 Pin Status The following table shows the status in each operating mode of the pins that have output functions. Table 2-10. Pin Status in Each Operating Mode (1/3) Pin Name Pin Status Note Reset Software Hardware HALT Mode Standby...
Page 51 CHAPTER 2 PIN FUNCTIONS Table 2-10. Pin Status in Each Operating Mode (2/3) Pin Name Pin Status Note Reset Software Hardware HALT Mode Standby Unit Test STOP Mode STOP Mode Test Mode Mode VSB pins VBDC Operates Undefined Operates VBDV Operates Undefined Operates...
Page 52 CHAPTER 2 PIN FUNCTIONS Table 2-10. Pin Status in Each Operating Mode (3/3) Pin Name Pin Status Note Reset Software Hardware HALT Mode Standby Unit Test STOP Mode STOP Mode Test Mode Mode Data IDDARQ Undefined Operates cache pins IDAACK Undefined Operates IRRSA...
Page 53: Chapter 3 Cpu
CHAPTER 3 CPU The CPU of the NU85E, which is based on a RISC architecture, executes almost all instructions in one clock cycle due to its five-stage pipeline control. 3.1 Features • Advanced 32-bit architecture for embedded control • Number of instructions: 83 •...
Page 54: Registers
CHAPTER 3 CPU 3.2 Registers The CPU registers can be classified into program registers, which are used by programs, and system registers, which are used to control the execution environment. All registers are 32-bit registers. Figure 3-1. List of CPU Registers (a) Program registers (b) System registers r0 (Zero register)
Page 55: Program Registers
CHAPTER 3 CPU 3.2.1 Program registers The program registers include the general-purpose registers (r0 to r31) and the program counter (PC). Table 3-1. List of Program Registers Program Register Name Function General-purpose Zero register (always holds zero) register Assembler-reserved register (used as a working register for address generation) Address/data variable register (when this register is not used by the real-time OS) Stack pointer (used to generate a stack frame when a function is called) Global pointer (used to access a global variable of the data area)
Page 56: Program Counter (Pc)
CHAPTER 3 CPU (2) Program counter This register holds the instruction address during program execution. The lower 26 bits are valid, and bits 31 to 26 are reserved for future function expansion (fixed at 0). If a carry from bit 25 to bit 26 occurs, it is ignored. Also, bit 0 is fixed at 0, and no branching to an odd address can be performed.
Page 57: System Registers
CHAPTER 3 CPU 3.2.2 System registers System registers control the status of the CPU and hold interrupt information. To read from or write to these system registers, specify the system register number (see Table 3-2) indicated by the system register load or store instruction (LDSR or STSR instruction). Table 3-2.
Page 58: Interrupt Source Register (Ecr)
CHAPTER 3 CPU Caution When interrupt servicing is performed and control is returned by the RETI instruction after bit 0 of the EIPC, FEPC, or CTPC had been set (1) by the LDSR instruction, bit 0 is ignored (because bit 0 of the PC is fixed at 0).
Page 59: Program Status Word (Psw)
CHAPTER 3 CPU Figure 3-4. Program Status Word (PSW) 8 7 6 5 4 3 2 1 0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z 00000020H Bit Position Bit Name...
Page 60: Address Space
CHAPTER 3 CPU 3.3 Address Space The CPU of the NU85E supports a linear address space with a maximum size of 4 GB. Memory and I/O are located in this address space (memory mapped I/O method). Figure 3-5. Address Space...
Page 61: Program Area
CHAPTER 3 CPU 3.3.1 Program area For instruction addressing, the CPU of the NU85E supports a linear address space (program area) with a maximum size of 64 MB. Figure 3-6. Program Area 3FFFFFFH Peripheral I/O area (4 KB) 3FFF000H 3FFEFFFH...
Page 62: Data Area
CHAPTER 3 CPU 3.3.2 Data area For operand addressing (data access), the CPU of the NU85E supports a linear address space (data area) with a maximum size of 4 GB. The ROM, RAM, and peripheral I/O areas are each located in 64 MB or 256 MB address spaces. The size setting is selected according to the input level to the IFID256 pin.
Page 63: Data Area (256 Mb Mode)
CHAPTER 3 CPU (2) 256 MB mode When a high-level signal is input to the IFID256 pin, the data area is set to 256 MB mode. In this mode, the 256 MB physical address space can be viewed as 16 images in the 4 GB address space. That is, the same 256 MB physical address space is accessed regardless of the values of bits 31 to 28 of the CPU address.
Page 64: Areas
The area where it is to be located is selected according to the input level to the IFIROB2 pin. (2) Interrupt/exception table The NU85E increases the interrupt response speed by assigning fixed jump destination addresses corresponding to interrupts or exceptions.
Page 65 CHAPTER 3 CPU Table 3-3. Interrupt/Exception Table Starting Address Interrupt/Exception Starting Address Interrupt/Exception Starting Address Interrupt/Exception Source Source Source 00000000H RESET 00000190H INT17 00000310H INT41 00000010H NMI0 000001A0H INT18 00000320H INT42 00000020H NMI1 000001B0H INT19 00000330H INT43 00000030H NMI2 000001C0H INT20 00000340H INT44...
Page 66: Ram Area
CHAPTER 3 CPU 3.4.2 RAM area In 64 MB mode, the area at address 3FFEFFFH and below is reserved as the area for RAM connected to the VDB. In 256 MB mode, the address at FFFEFFFH and below is reserved. The size of the RAM area, which can be selected from among 4 KB, 12 KB, 28 KB, and 60 KB, is set according to the input levels to the IFRA64, IFRA32, and IFRA16 pins.
Page 67: Peripheral I/O Area
Peripheral I/O registers to which functions have been assigned such as status monitoring or specification of the operating mode of the NU85E, memory controller (MEMC), or instruction/data cache are located in this area. For information about assigned registers, see 3.5 Peripheral I/O Registers.
Page 68: Peripheral I/O Area
Reserved area Peripheral (MEMC control register) I/O area xFFF480H xFFF47FH User-usable area xFFF200H xFFF1FFH xFFF100H xFFF0FFH Reserved area (NU85E control register) xFFF080H xFFF07FH Reserved area (instruction/data cache control register) xFFF070H xFFF06FH Reserved area (NU85E control register) xFFF060H xFFF05FH Reserved area...
Page 69: External Memory Area
(2n) will be accessed. (3) Although word-accessible registers do not exist in the NU85E, halfword access using the lower and higher bits (in that order and ignoring the lowest 2) of a word area can be made twice to enable word access.
Page 70: Nu85E Control Registers
CHAPTER 3 CPU 3.5.1 NU85E control registers (1/4) Address Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ FFFFF060H Chip area select control register 0 CSC0 2C11H √ FFFFF062H Chip area select control register 1...
Page 71 CHAPTER 3 CPU (2/4) Address Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ FFFFF0F2H DMA restart register DRST √ FFFFF100H Interrupt mask register 0 IMR0 FFFFH √ √ FFFFF100H Interrupt mask register 0L IMR0L √...
Page 72 CHAPTER 3 CPU (3/4) Address Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ FFFFF142H Interrupt control register 25 PIC25 √ √ FFFFF144H Interrupt control register 26 PIC26 √ √ FFFFF146H Interrupt control register 27 PIC27 √...
Page 73: Memory Controller (Memc) Control Registers
CHAPTER 3 CPU (4/4) Address Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ FFFFF18EH Interrupt control register 63 PIC63 √ √ FFFFF1FAH In-service priority register ISPR √ FFFFF1FCH Command register PRCMD Undefined √...
Page 74: Instruction Cache Control Registers
CHAPTER 3 CPU 3.5.3 Instruction cache control registers Address Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ Note 1 FFFFF070H Instruction cache control register 0003H √ √ Note 2 FFFFF070H Instruction cache control register L ICCL √...
Page 75: Rcu Interface
(address mask), or 2-stage sequential execution, as well as a break interrupt function operable by external port input. Connection of the RCU to the NU85E allows not only debugging using these functions, but also makes possible the employment of a background monitor JTAG system ROM emulator and an N- Wire type in-circuit emulator.
Page 76: Chapter 4 Bcu
CHAPTER 4 BCU The bus control unit (BCU), which operates as a bus master on the VSB, controls the on-chip bus bridge (BBR), test interface control unit (TIC), and peripheral macros (bus slaves) such as the external memory controller (MEMC) connected to the VSB.
Page 77 CHAPTER 4 BCU (1) Memory banks for 64 MB mode The 64 MB data area is subdivided into memory banks with sizes of 2 MB, 4 MB, and 8 MB. 3FFFFFFH 3FFFFFFH Bank 15 Peripheral I/O area (2 MB) (4 KB) 3E00000H 3DFFFFFH 3FFF000H...
Page 78 CHAPTER 4 BCU (2) Memory banks for 256 MB mode The 256 MB data area is subdivided into four areas (area 0 to area 3), each of which contain memory banks of size 2 MB. FFFFFFFH FFFFFFFH Bank 15 Peripheral I/O area (2 MB) (4 KB) FE00000H...
Page 79: Programmable Chip Select Function
CHAPTER 4 BCU 4.3 Programmable Chip Select Function The VDCSZn signals corresponding to each bank of memory are set and the data area is subdivided into multiple CSn areas according to the chip area select control registers 0 and 1 (CSC0 and CSC1) (n = 7 to 0). The CSC0 and CSC1 registers can be read or written in 16-bit units.
Page 80: Chip Area Select Control Register 1 (Csc1)
CHAPTER 4 BCU Figure 4-2. Chip Area Select Control Register 1 (CSC1) Address After reset CSC1 FFFFF062H 2C11H Bit position Bit name Function 15 to 0 CSn3 to When each bit is set (1), the VDCSZn signal becomes active if the condition within CSn0 parentheses holds.
Page 81: Csc0 And Csc1 Register Setting Example (64 Mb Mode)
CHAPTER 4 BCU Examples 1. The following figure shows an example of CSC0 and CSC1 register settings for 64 MB mode and the memory map after the settings are made. Figure 4-3. CSC0 and CSC1 Register Setting Example (64 MB Mode) (1/3) (a) CSC0 register settings 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSC0...
Page 82 CHAPTER 4 BCU Figure 4-3. CSC0 and CSC1 Register Setting Example (64 MB Mode) (2/3) (b) CSC1 register settings 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSC1 1 0 1 1 1 1 1 1 0 0 VDCSZn signals that become active VDCSZ7 (when accessing bank 14) VDCSZ7 (when accessing bank 13)
Page 83 CHAPTER 4 BCU Figure 4-3. CSC0 and CSC1 Register Setting Example (64 MB Mode) (3/3) (c) Memory map Bank 15 (2M) [VDCSZ5] CS5 area Bank 14 (2M) [VDCSZ7] CS7 area Bank 13 (2M) [VDCSZ7] Bank 12 (2M) [VDCSZ6] Bank 11 (4M) [VDCSZ6] CS6 area Bank 10 (4M) [VDCSZ6] Bank 9 (8M)
Page 84: Csc0 And Csc1 Register Setting Example (256 Mb Mode)
CHAPTER 4 BCU Examples 2. The following figure shows an example of CSC0 and CSC1 register settings for 256 MB mode and the memory map after the settings are made. Figure 4-4. CSC0 and CSC1 Register Setting Example (256 MB Mode) (1/2) (a) CSC0 register settings 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSC0...
Page 85: Programmable Peripheral I/O Area Selection Function
4.4 Programmable Peripheral I/O Area Selection Function The NU85E has a 4 KB peripheral I/O area that is allocated in advance in the address space and a 12 KB programmable peripheral I/O area that can be allocated at arbitrary addresses according to register settings.
Page 86: Peripheral I/O Area And Programmable Peripheral I/O Area
CHAPTER 4 BCU Figure 4-5. Peripheral I/O Area and Programmable Peripheral I/O Area (a) 64 MB mode (b) 256 MB mode 3FFFFFFH FFFFFFFH Peripheral I/O area Peripheral I/O area Same Same (4 KB) (4 KB) 3FFF000H FFFF000H area area 3FFEFFFH FFFEFFFH Same (RAM area)
Page 87: Peripheral I/O Area Select Control Register (Bpc)
CHAPTER 4 BCU The programmable peripheral I/O area can be used by specifying the higher 14 bits (bit 27 to bit 14) of the starting address in the PA00 to PA13 bits of the peripheral I/O area select control register (BPC) and setting (1) the PA15 bit. The BPC register can be read or written in 16-bit units.
Page 88: Bus Size Setting Function
CHAPTER 4 BCU 4.5 Bus Size Setting Function The bus size setting function uses the bus size configuration register (BSC) to set the VSB data bus size for each CSn area selected by the chip select signals (VDCSZn) (see Figures 4-3 and 4-4) (n = 7 to 0). The BSC register can be read or written in 16-bit units.
Page 89: Endian Setting Function
CHAPTER 4 BCU 4.6 Endian Setting Function 4.6.1 Endian configuration register (BEC) The endian setting function uses the endian configuration register (BEC) to set the endian format of word data within memory for each CSn area selected by the chip select signals (VDCSZn) (see Figures 4-3 and 4-4) (n = 7 to The BEC register can be read or written in 16-bit units.
Page 90: Usage Restrictions Concerning Big Endian Format With Nec Development Tools
CHAPTER 4 BCU Figure 4-9. Word Data Little Endian Format Example 16 15 (000BH) (000AH) (0009H) (0008H) (0007H) (0006H) (0005H) (0004H) (0003H) (0002H) (0001H) (0000H) Figure 4-10. Word Data Big Endian Format Example 16 15 (0008H) (0009H) (000AH) (000BH) (0004H) (0005H) (0006H) (0007H)
Page 91 CHAPTER 4 BCU However, it is unnecessary to specify the above optimization suppression options when not using “cast” Note or “mask/shift” access Note The condition is that patterns causing the following optimization are not used. It is extremely difficult to perform a perfect check on the user side in a state such as where all the patterns (especially in the model-based optimization section) are mixed together.
Page 92: Cache Configuration
CHAPTER 4 BCU 4.7 Cache Configuration The cache configuration register (BHC) is used to set the cache memory configuration for each CSn area selected by the chip select signals (VDCSZn) (see Figures 4-3 and 4-4) (n = 7 to 0). The BHC register can be read or written in 16-bit units.
Page 93: Bcu-Related Register Setting Examples
CHAPTER 4 BCU 4.8 BCU-Related Register Setting Examples Figure 4-12 shows a BPC, BSC, BEC, and BHC register setting example, the corresponding settings for each CSn area, and the memory map when the data area has been set according to the contents of the example shown in Figure 4-3 CSC0 and CSC1 Register Setting Example (64 MB Mode) (n = 7 to 0).
Page 94 CHAPTER 4 BCU Figure 4-12. BPC, BSC, BEC, BHC Register Setting Example (2/3) (d) BHC register setting %+& ,QVWUXFWLRQ FDFKH VHWWLQJ RI &6Q DUHD &6 DUHD &DFKH QRW DYDLODEOH &6 DUHD &DFKH DYDLODEOH...
Page 95 CHAPTER 4 BCU Figure 4-12. BPC, BSC, BEC, BHC Register Setting Example (3/3) (f) Memory map 3FFFFFFH Bank 15 CS5 area 3E00000H 3DFFFFFH Bank 14 3C00000H CS7 area 3BFFFFFH Bank 13 3A00000H 39FFFFFH Bank 12 3800000H 37FFFFFH Bank 11 CS6 area 3400000H 33FFFFFH Bank 10...
Page 96: Data Transfer Using Vsb
(Bus master 1) VAREQ <1> The NU85E grants bus control (bus access right) to only one bus master according to the on-chip bus arbiter (Refer to 4.9.5 Bus master transition for detail). The bus arbiter arbitrates the bus access right according to the following prioritization.
Page 97: Control Signals Output By Bus Master
4.9.2 Control signals output by bus master When the NU85E operates as the bus master, the contents of the transfer that is currently being executed are indicated by outputting the various control signals indicated below (When the NU85E operates as a bus slave, the external bus master performs output, and this data is input to the NU85E as the VSxxxx signal).
Page 98 CHAPTER 4 BCU (3) Byte enable The bus master uses the VMBENZ3 to VMBENZ0 signals to indicate the byte data among the data obtained by quartering the data bus (VBDI31 to VBDI0 and VBDO31 to VBDO0) into byte units. Table 4-3. VMBENZ3 to VMBENZ0 Signals Active (Low-Level Output) Signal Enabled Byte Data VMBENZ0...
Page 99 CHAPTER 4 BCU (6) Transfer response The transfer response is indicated by the VMWAIT, VMAHLD, and VMLAST signals, which are output from the bus slave (The signal names on the bus slave side are VSWAIT, VSAHLD, and VSLAST). These signals become effective only while the VBCLK signal is low level.
Page 100: Read/Write Timing
(samples) the data in synchronization with the next falling edge of the VBCLK signal. (2) Write timing Write data is output from the NU85E in synchronization with the falling edge of the VBCLK signal half clock after the address is output to the bus slave.
Page 101: Read/Write Timing Of Bus Slave Connected To Vsb
Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (1/12) (a) 32-bit bus (single transfer, no waits) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (0,0) (1,0) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) (0,0,0,0) (1,1,1,1) (0,0,0,0)
Page 102 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (2/12) (b) 32-bit bus (single transfer, 1 wait inserted) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (0,0) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1)
Page 103 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (3/12) (c) 32-bit bus (single transfer, 2 waits inserted) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (0,0) (1,0) (1,1) (1,0) (1,1) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) VMWRITE (Output)
Page 104 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (4/12) (d) 32-bit bus (single transfer, 2 waits inserted, with address hold) Read Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) (0,0,0,0)
Page 105 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (5/12) (e) 32-bit bus (4-word sequential transfer, data access) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (0,0) (1,0) (1,1) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) VMWRITE (Output) (0,0,0,0) VMBENZ3 to VMBENZ0 (Output)
Page 106 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (6/12) (f) 16-bit bus (4-word sequential transfer, data access) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (0,0) (1,0) (1,1) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) A.10 A.11 A.12...
Page 107 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (7/12) (g) 8-bit bus (4-byte sequential transfer, external ROM fetch) Read Idle Read Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (0,0) (1,0) (1,1) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) VMWRITE (Output) (1,1,1,0) VMBENZ3 to VMBENZ0 (Output)
Page 108 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (8/12) (h) 32-bit bus (little-endian, word/halfword/byte transfer) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (0,0) (1,0) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) A.10 A.11 A.12 A.13 VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) (0,0,0,0) (1,1,0,0)
Page 109 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (9/12) (i) 32-bit bus (big-endian, word/halfword/byte transfer) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (0,0) (1,0) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) A.10 A.11 A.12 A.13 VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) (0,0,0,0) (0,0,1,1)
Page 110 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (10/12) (j) 16-bit bus (little-endian, word/halfword/byte transfer) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (0,0) (1,0) (1,1) (1,0) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) A.10 A.11 A.12...
Page 111 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (11/12) (k) 16-bit bus (big-endian, word/halfword/byte transfer) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (0,0) (1,0) (1,1) (1,0) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) A.10 A.11 A.12...
Page 112 Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (12/12) (l) 8-bit bus (little/big-endian, word/halfword/byte transfer) Read Idle Write Idle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) (1,0) (0,0) (1,0) (1,1) (1,0) (1,1) (1,0) (0,0) VMLOCK (Output) VMA27 to VMA0 (Output) A.10...
Page 113: Vsb Read/Write Timing Example
CHAPTER 4 BCU 4.9.4 VSB read/write timing example The read/write timing example of SRAM connected to the NT85E500 is shown below. Figure 4-15. VSB Timing Example (1/2) (a) VSB read timing example Read Read VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (0,0) (1,0)
Page 114 CHAPTER 4 BCU Figure 4-15. VSB Timing Example (2/2) (b) VSB write timing example Write Write Write VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (1,1) (1,0) (1,1) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) 00000000H VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output)
Page 115: Reset Timing
A.x: Arbitrary address output from the VMA27 to VMA0 pins D.x: Input data from address “A.x” Arbitrary input level 2. The timing seen from the NU85E when the NU85E has the bus access right is shown. Preliminary User’s Manual A14874EJ3V0UM...
Page 116: Bus Master Transition
CHAPTER 4 BCU 4.9.6 Bus master transition There are five kinds of external bus cycles as shown below. Bus hold has the highest priority, followed by refresh cycle, DMA cycle, operand data access, and instruction fetch in that order. Priority External Bus Cycle Bus Master High...
Page 117: Bus Master Transition Timing
CHAPTER 4 BCU Figure 4-17. Bus Master Transition Timing Bus master <1> <2> <3> <4> <5> <6> VBCLK (Input) VAREQ (Input) VAACK (Output) VMLOCK (Output) VMTTYP1, VMTTYP0 (Output) (1,0) VMA27 to VMA0 (Output) VMWRITE, VMBENZ3 to VMBENZ0, VMCTYP2 to VMCTYP0, VMSIZE1, Ctrl.2 Ctrl.3 VMSIZE0, VMSEQ2 to VMSEQ0,...
Page 118: Misalign Access Timing
VBDO31 to VBDO0 56780000H 00001234H (Output) VMWAIT (Input) VMAHLD (Input) VMLAST (Input) Remarks 1. O mark: Sampling timing Arbitrary input level 2. The timing seen from the NU85E when the NU85E has the bus access right is shown. Preliminary User’s Manual A14874EJ3V0UM...
Page 119 78xxxxxxH xxxx3456H xx12xxxxH (Output) VMWAIT (Input) VMAHLD (Input) VMLAST (Input) Remarks 1. O mark: Sampling timing Arbitrary input level 2. The timing seen from the NU85E when the NU85E has the bus access right is shown. Preliminary User’s Manual A14874EJ3V0UM...
Page 120: Chapter 5 Bbr
The BBR sets up the following functions for peripheral macros that are connected to the NPB. • Wait insertion function • Retry function Figure 5-1. NPB Connection Overview VSB (high speed) Peripheral Peripheral macro (1) macro (2) NPB (low speed) NU85E Peripheral Peripheral macro (3) macro (4) Preliminary User’s Manual A14874EJ3V0UM...
Page 121: Nu85E And Peripheral Macro Connection Example
CHAPTER 5 BBR The following figure shows a connection example connecting the NU85E and peripheral macros that are connected to the NPB. Figure 5-2. NU85E and Peripheral Macro Connection Example NU85E VPA13 to VPA0 Note VPAn to VPA0 VPCS Address...
Page 122: Programmable Peripheral I/O Area
5.1 Programmable Peripheral I/O Area The NU85E has a 4 KB peripheral I/O area that is allocated in advance in the address space and a 12 KB programmable peripheral I/O area that can be allocated at arbitrary addresses according to register settings (See 4.4 Programmable Peripheral I/O Area Selection Function).
Page 123: Peripheral I/O Area Select Control Register (Bpc)
CHAPTER 5 BBR Figure 5-4. Peripheral I/O Area Select Control Register (BPC) Address After reset FFFFF064H 0000H Bit position Bit name Function PA15 Sets whether or not the programmable peripheral I/O area can be accessed. 0: It cannot be accessed 1: It can be accessed 13 to 0 PA13 to...
Page 124: Bpc Register Setting Example
CHAPTER 5 BBR Figure 5-5. BPC Register Setting Example (a) BPC register setting 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 0 0 Programmable peripheral I/O area starting address: 2400000H Programmable peripheral I/O area: Can be accessed...
Page 125: Wait Insertion Function
CHAPTER 5 BBR 5.2 Wait Insertion Function The BBR is equipped with a wait insertion function for connection with low-speed peripheral macros that are connected to the NPB. The NPB strobe wait control register (VSWC) is used to set up this function. The VSWC register sets the setup wait length and VPSTB wait length (see Figure 5-6).
Page 126 CHAPTER 5 BBR Figure 5-6. NPB Strobe Wait Control Register (VSWC) (2/2) Bit position Bit name Function 2 to 0 VSWL2 to Sets the VPSTB wait length. VSWL0 VSWL2 VSWL1 VSWL0 VPSTB wait length 0 (no waits) 1×t 2×t 3×t 4×t 5×t 6×t...
Page 127: Retry Function
CHAPTER 5 BBR 5.3 Retry Function The retry function, which repeats read or write processing according to a retry request signal (VPRETR) from a peripheral macro on the NPB, is used in situations such as when the data setup time is insufficient. If a high-level signal is being input to the VPRETR and VPDACT pins at the falling edge of the VPSTB signal, the VPSTB signal rises again and the read or write operation is repeated.
Page 128: Npb Read/Write Timing
Figure 5-8 to Figure 5-13 show the basic read/write timing of NPB, Figure 5-14 shows a timing example for read/write access to a bus slave connected to the NU85E and NPB, and Figure 5-15 shows a timing example of write access to a peripheral I/O register.
Page 129: Timing Of Byte Access To Odd Address
CHAPTER 5 BBR Figure 5-9. Timing of Byte Access to Odd Address Write cycle Read cycle VPA13 to VPA0 (Output) VPDO15 to VPDO8 (Output) VPDI15 to VPDI8 (Input) VPDO7 to VPDO0 (Output) VPDI7 to VPDI0 (Input) VPWRITE (Output) VPSTB (Output) VPUBENZ (Output) VPLOCK (Output) VPRETR (Input)
Page 130: Read Modify Write Timing
CHAPTER 5 BBR Figure 5-11. Read Modify Write Timing Idle cycle Read cycle Write cycle VPA13 to VPA0 Address Address (Output) VPDO15 to VPDO0 Data (Output) VPDI15 to VPDI0 Data (Input) VPWRITE (Output) VPSTB (Output) VPUBENZ (Output) VPLOCK (Output) VPRETR (Input) Remark The VPLOCK signal becomes active during a read operation.
Page 131: Retry Timing (Read)
CHAPTER 5 BBR Figure 5-13. Retry Timing (Read) VPA13 to VPA0 Address (Output) VPDI15 to VPDI0 Data Data (Input) VPWRITE (Output) VPSTB (Output) VPUBENZ (Output) VPLOCK (Output) VPRETR (Input) VPDACT (Input) Remark If the VPRETR and VPDACT signals are high level at the falling edge of the VPSTB signal, the VPSTB signal becomes active, and the read operation is performed again.
Page 132: Read/Write Timing Of Bus Slave Connected To Npb
Figure 5-14. Read/Write Timing of Bus Slave Connected to NPB (1/4) (a) Example of timing of word-data write to NPB peripheral macro (programmable peripheral I/O area) VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (1,1) VMLOCK (Output) VMA27 to VMA0 (Output) 2403800H 2403802H VMWRITE (Output)
Page 133 Figure 5-14. Read/Write Timing of Bus Slave Connected to NPB (2/4) (b) Example of timing of halfword-data write to NPB peripheral macro (programmable peripheral I/O area) VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (1,1) VMLOCK (Output) VMA27 to VMA0 (Output) 2403804H 2403806H VMWRITE (Output)
Page 134 Figure 5-14. Read/Write Timing of Bus Slave Connected to NPB (3/4) (c) Example of timing of word-data read from NPB peripheral macro (programmable peripheral I/O area) VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (1,1) VMLOCK (Output) VMA27 to VMA0 (Output) 2403800H 2403802H VMWRITE (Output)
Page 135 Figure 5-14. Read/Write Timing of Bus Slave Connected to NPB (4/4) (d) Example of timing of halfword-data read from NPB peripheral macro (programmable peripheral I/O area) VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (1,0) (1,1) (1,0) (1,1) VMLOCK (Output) VMA27 to VMA0 (Output) 2403804H 2403806H VMWRITE (Output)
Page 136: Npb Write Timing (Example Of Timing Of Data Write To Csc0 And Csc1 Registers)
Figure 5-15. NPB Write Timing (Example of Timing of Data Write to CSC0 and CSC1 Registers) VBCLK (Input) VMTTYP1, VMTTYP0 (Output) (0,0) (1,0) (1,1) (0,0) (1,0) (1,1) (0,0) VMA27 to VMA0 (Output) 0000000H 3FFF060H 0000000H 3FFF062H 0000000H VBDO31 to VBDO0 (Output) 00000000H 00002C11H 00000000H...
Page 137: Precautions
BBR does not provide a bus sizing function. Therefore, NPB access from the external bus master of the VSB to the NU85E as a slave must be executed with the bus size of the VSB set to 16 bits. Preliminary User's Manual A14874EJ3V0UM...
Page 138: Chapter 6 Stbc
CHAPTER 6 STBC The standby control unit (STBC) implements the various power save functions of the NU85E by controlling the external clock generator (CG). 6.1 Power Save Function The power save function has the following three modes. (1) HALT mode This mode, which stops the supply of clocks only to the CPU, is set by executing a special-purpose instruction (HALT instruction).
Page 139: Control Registers
CHAPTER 6 STBC 6.2 Control Registers 6.2.1 Power save control register (PSC) The PSC is an 8-bit register that controls the power save function. If interrupts are enabled according to the NMI2M to NMI0M and INTM bit settings, software STOP mode can be canceled by an interrupt request (except when interrupt servicing is disabled by the interrupt mask register (IMR0 to IMR3)).
Page 140 PRCMD register). • Store instruction (ST or SST instruction) • Bit manipulation instruction (SET1, CLR1, or NOT1 instruction) <4> If the NU85E switches to software STOP mode, insert NOP instructions (five or more instructions). Examples 1. <1> mov 0x02, r11 movea base_address, r0, r20 ;...
Page 141: Command Register (Prcmd)
CHAPTER 6 STBC Remarks 5. The following shows the operation when a non-maskable interrupt or maskable interrupt is requested while a NOP instruction is being executed. • If a non-maskable or maskable interrupt is requested before SWSTOPRQ becomes active, the interrupt servicing is immediately executed.
Page 142: Halt Mode
The NU85E is switched to HALT mode by the HALT instruction. Although program execution stops in HALT mode, the contents of all registers and of RAM immediately before HALT mode began are maintained. Also, operation continues for all NU85E-internal peripheral I/O that does not depend on CPU instruction processing.
Page 143: Software Stop Mode
(1) Setting and operation status The NU85E is switched to software STOP mode by using a store instruction (ST or SST instruction) or bit manipulation instruction (SET1, CLR1, or NOT1 instruction) to set the PSC register.
Page 144 CHAPTER 6 STBC Table 6-3. Operation After Setting Software STOP Mode in Interrupt Servicing Routine Interrupt Servicing Routine Type Cancellation Source Operation When Software STOP Mode Is Set Note 1 Priority Maskable interrupt Maskable Software STOP mode is canceled interrupt and the interrupt request is not Same request...
Page 145: Hardware Stop Mode
The NU85E is switched to hardware STOP mode by inputting a low-level signal to the DCSTOPZ pin. The NU85E is switched to hardware STOP mode even if a low-level signal is input to the DCSTOPZ pin when the NU85E is in HALT mode or software STOP mode.
Page 146: Clock Control In Software/Hardware Stop Mode
Note Design the clock control circuit as a user logic. Also, include a circuit for ensuring the oscillation stabilization time (see Figures 6-5 and 6-6). Caution In a system in which the MEMC is not connected to the NU85E, handle the STPAK pin in either of the following ways.
Page 147 CHAPTER 6 STBC (1) Clock control when setting or canceling software STOP mode (a) When setting software STOP mode (after software STOP mode is set by setting the STP bit of the PSC register) <1> Set the STOP mode request signal (STPRQ) to active (high level) and output it to the memory controller.
Page 148: Software Stop Mode Set/Cancel Timing Example
CHAPTER 6 STBC Figure 6-5. Software STOP Mode Set/Cancel Timing Example (a) When software STOP mode is canceled by DCNMIm or INTn input VBCLK (Input) STPRQ (Output) STPAK (Input) SWSTOPRQ (Output) DCNMIm (Input) INTn (Input) CGREL (Input) Oscillation stabilization time 1 clock or more Remarks 1.
Page 149 CHAPTER 6 STBC (2) Clock control when setting or canceling hardware STOP mode (a) When setting hardware STOP mode <1> Input the active level (low level) of the DCSTOPZ signal. <2> Set the STOP mode request signal (STPRQ) to active (high level) and output it to the memory controller.
Page 150: Hardware Stop Mode Set/Cancel Timing Example
CHAPTER 6 STBC Figure 6-6. Hardware STOP Mode Set/Cancel Timing Example (a) When hardware STOP mode is canceled by DCSTOPZ input VBCLK (Input) STPRQ (Output) STPAK (Input) HWSTOPRQ (Output) DCSTOPZ (Input) Oscillation stabilization time CGREL (Input) 1 clock or more (b) When hardware STOP mode is canceled by DCRESZ input VBCLK (Input) STPRQ (Output)
Page 151: Chapter 7 Dmac
CHAPTER 7 DMAC The DMA control unit (DMAC) controls data transfers between memory and peripheral macros or between memory and memory based on DMA transfer requests issued according to the DMARQ3 to DMARQ0 pins or software triggers (memory means RAM or external memory). 7.1 Features •...
Page 152: Configuration
CHAPTER 7 DMAC 7.2 Configuration Peripheral macro NU85E DMA source address register Data Address (DSAnH/ DSAnL) control control DMA destination address register (DDAnH/ DDAnL) Count DMA transfer count register DMTCOn control (DBCn) IDMASTP DMA channel control register (DCHCn) DMARQn Channel...
Page 153: Transfer Objects
CHAPTER 7 DMAC 7.3 Transfer Objects (1) Transfer types Table 7-1 shows the relationships between transfer types and transfer objects. Caution Operation is not guaranteed when a transfer is performed using a combination of transfer source and transfer destination marked by an “No” in Table 7-1. Table 7-1.
Page 154: Control Registers
CHAPTER 7 DMAC 7.5 Control Registers 7.5.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA transfer source addresses (28 bits each) for DMA channels n (n = 0 to 3). They are divided into two 16-bit registers, DSAnH and DSAnL, respectively.
Page 155: Dma Source Address Registers 0L To 3L (Dsa0L To Dsa3L)
CHAPTER 7 DMAC (2) DMA source address registers 0L to 3L (DSA0L to DSA3L) These registers can be read or written in 16-bit units. Figure 7-2. DMA Source Address Registers 0L to 3L (DSA0L to DSA3L) Address After reset DSA0L FFFFF080H Undefined Address...
Page 156: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
CHAPTER 7 DMAC 7.5.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA transfer destination addresses (28 bits each) for DMA channels n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL, respectively. Since they are two-stage FIFO-configuration buffer registers, the transfer destination address of a new DMA transfer can be set during a DMA transfer (See 7.6 Next Address Setting Function).
Page 157: Dma Destination Address Registers 0L To 3L (Dda0L To Dda3L)
CHAPTER 7 DMAC (2) DMA destination address registers 0L to 3L (DDA0L to DDA3L) These registers can be read or written in 16-bit units. Figure 7-4. DMA Destination Address Registers 0L to 3L (DDA0L to DDA3L) Address After reset DDA0L FFFFF084H Undefined Address...
Page 158: Dma Transfer Count Registers 0 To 3 (Dbc0 To Dbc3)
CHAPTER 7 DMAC 7.5.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the transfer counts for DMA channels n (n = 0 to 3). These registers maintain the remaining transfer count during a DMA transfer. Since they are two-stage FIFO-configuration buffer registers, the transfer count of a new DMA transfer can be set during a DMA transfer (See 7.6 Next Address Setting Function).
Page 159: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
CHAPTER 7 DMAC 7.5.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer operation mode for DMA channels n (n = 0 to 3). These registers can be read or written in 16-bit units. Caution These registers cannot be accessed during a DMA transfer.
Page 160 CHAPTER 7 DMAC Figure 7-6. DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3) (2/2) Bit position Bit name Function 7, 6 SAD1, Sets the count direction of the transfer source addresses for DMA channels n (n = 0 to 3). SAD0 SAD1 SAD0...
Page 161: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
CHAPTER 7 DMAC 7.5.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operation mode for DMA channels n (n = 0 to 3). These registers can be read or written in 8-bit or 1-bit units (However, bit 7 can only be read and bits 2 and 1 can only be written.
Page 162: Dma Disable Status Register (Ddis)
CHAPTER 7 DMAC Figure 7-7. DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3) (2/2) Bit position Bit name Function Sets whether DMA transfer is enabled or disabled for DMA channel n. This bit is cleared (0) when the DMA transfer is completed. It is also cleared (0) when an IDMASTP signal is input or when transfer is forcibly terminated by setting (1) the INITn bit.
Page 163: Dma Restart Register (Drst)
CHAPTER 7 DMAC 7.5.7 DMA restart register (DRST) This register is used to restart a DMA transfer that was forcibly interrupted by inputting an IDMASTP signal. The ENn bits of this register are linked respectively with the ENn bits of the DCHCn registers (n = 0 to 3). After a DMA transfer was forcibly interrupted by inputting the IDMASTP signal, the DMA channel for which the transfer was interrupted is confirmed from the contents of the DDIS register, and the DMA transfer can be restarted by setting (1) the ENn bit of the corresponding DMA channel.
Page 164: Next Address Setting Function
CHAPTER 7 DMAC 7.6 Next Address Setting Function The DMA source address registers (DSAnH and DSAnL), DMA destination address registers (DDAnH and DDAnL), and DMA transfer count registers (DBCn) are two-stage FIFO-configuration buffer registers (n = 0 to 3). When a terminal count signal (DMTCOn) is output, these registers are automatically rewritten with the values that had just been set before the signal is output.
Page 165: Dma Bus State
CHAPTER 7 DMAC 7.7 DMA Bus State 7.7.1 Bus state types DMAC bus cycles consist of the 13 states shown below. (1) TI state This is an idle state in which there is no access request. The DMARQ3 to DMARQ0 signals are sampled at the rising edge of the VBCLK signal. (2) T0 state This is a DMA transfer ready state (There is a DMA transfer request, and the bus access right has been acquired for the first DMA transfer).
Page 166 CHAPTER 7 DMAC (11) T1FHI state This is the last state of a flyby transfer, and the DMAC is awaiting the end of the transfer. After the T1FHI state, the bus is released, and the DMAC transitions to the TE state. (12) T2FH state This is the state in which the DMAC judges whether or not to continue flyby transfers.
Page 167: Dmac Bus Cycle State Transitions
CHAPTER 7 DMAC 7.7.2 DMAC bus cycle state transitions Figure 7-11. DMAC Bus Cycle State Transition Diagram (a) Two-cycle transfer (b) Flyby transfer T1RI T1FH T2RI T1WI T2FH T1FHI Preliminary User’s Manual A14874EJ3V0UM...
Page 168: Transfer Modes
CHAPTER 7 DMAC 7.8 Transfer Modes 7.8.1 Single transfer mode In single transfer mode, the DMAC releases the bus after each byte, halfword, or word transfer. If there is a subsequent DMA transfer request, a single transfer is performed again. This operation continues until a terminal count occurs.
Page 169: Single Transfer Example 3
CHAPTER 7 DMAC Figure 7-14 shows a single transfer mode example in which a lower priority DMA transfer request is generated within one clock after the end of a single transfer. DMA channels 0, 3 are used for a single transfer. When two DMA transfer request signals are activated at the same time, the two DMA transfers are performed alternately.
Page 170: Single-Step Transfer Mode
CHAPTER 7 DMAC 7.8.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus after each byte, halfword, or word transfer. Once a DMA transfer request signal (DMARQ3 to DMARQ0) is received, this operation continues until a terminal count occurs. If a higher priority DMA transfer request is generated while the DMAC has released the bus, the higher priority DMA transfer request always takes precedence.
Page 171: Line Transfer Mode
CHAPTER 7 DMAC 7.8.3 Line transfer mode In line transfer mode, the DMAC releases the bus after every four byte, halfword, or word transfers. If there is a subsequent DMA transfer request, four transfers are performed again. This operation continues until a terminal count occurs.
Page 172: Line Transfer Example 3
CHAPTER 7 DMAC Figures 7-20 and 7-21 show line transfer mode examples in which a lower priority DMA transfer request is generated within one clock after the end of a line transfer. When two DMA transfer request signals are activated at the same time, the two DMA transfers are performed alternately.
Page 173: Block Transfer Mode
CHAPTER 7 DMAC 7.8.4 Block transfer mode In block transfer mode, once transfer begins, the transfers continue without releasing the bus until a terminal count occurs. No other DMA transfer requests are acknowledged during a block transfer. After the block transfer ends and the DMAC has released the bus, another DMA transfer can be acknowledged. Although it is prohibited to insert a CPU bus cycle during a block transfer, bus mastership can be transferred even during a block transfer in response to a request by the external bus master (including SDRAM refresh).
Page 174: One-Time Transfer When Executing Single Transfers Using Dmarqn Signal
CHAPTER 7 DMAC 7.8.5 One-time transfer when executing single transfers using DMARQn signal (1) Two-cycle transfer When executing single transfers to the external memory using the DMARQn signal input, the next DMARQn signal is acknowledged when its sampling is started at the rise of VBCLK three clocks following the completion of the write cycle of the current 2-cycle transfer.
Page 175: Transfer Types
The signals indicating 2-cycle DMA transfer (1, 1, 0) are output from the VMCTYP2 to VMCTYP0 pins. Caution A one-clock idle cycle is always inserted between a read cycle and a write cycle. Figure 7-24. Example of Two-Cycle Transfer Memory NU85E NT85E500 (transfer source) A25 to A0...
Page 176: Flyby Transfer
Caution When NA85E535 is used as a memory controller, flyby transfer with SDRAM is possible, except in a system in which the SDRAM controller (NT85E502) is connected to the NT85E500. Figure 7-25. Example of Flyby Transfer (Memory to I/O) Memory NU85E NT85E500 (transfer source) A25 to A0...
Page 177: Dma Transfer Start Factors
CHAPTER 7 DMAC 7.10 DMA Transfer Start Factors DMA transfer can be started by the following two factors. (1) Request by external pin (DMARQn) If the ENn bit of the DCHCn register is set to 1 and the TCn bit is set to 0, the DMARQn signal becomes active in TI state (n = 3 to 0).
Page 178: Terminal Count Output When Dma Transfer Is Complete
CHAPTER 7 DMAC 7.11 Terminal Count Output When DMA Transfer Is Complete The terminal count signal (DMTCOn) becomes active for only one clock in the final DMA transfer cycle (n = 3 to 0). Figure 7-26. Timing Example of Terminal Count Signals (DMTCO3 to DMTCO0) DMARQn (Input) DMTCOn (Output) CPU DMAn DMAn DMAn...
Page 179: Forcible Interruption
CHAPTER 7 DMAC 7.12 Forcible Interruption DMA transfer can be forcibly interrupted by inputting the IDMASTP signal during the DMA transfer. At this time, the DMAC clears (0) the ENn bit of the DCHCn register of all channels to set the state in which DMA transfer is disabled, completes the DMA transfer that was being executed when the IDMASTP signal was input, and the bus releases to the CPU (n = 0 to 3).
Page 180: Forcible Termination
CHAPTER 7 DMAC 7.13 Forcible Termination By setting (1) the INITn bit of the DCHCn register during a DMA transfer, it is possible to forcibly terminate the DMA transfer under execution. The following is an example of the operation of a forcible termination (n = 0 to 3). Caution The setting (1) of the INITn bit is performed when the VSB has been released to the CPU (n = 0 to 3).
Page 181 CHAPTER 7 DMAC Figure 7-29. DMA Transfer Forcible Termination Example (2/2) (b) The transfer is forcibly terminated during block transfer using DMA channel 1 and a transfer with another condition is executed DSA1, DDA1, DBC1, DSA1, DDA1, DCHC1 DADC1, DADC1, DCHC1 DBC1 (INIT1 bit = 1) DCHC1...
Page 182: Dma Transfer Timing Examples
Examples of the DMA transfer timing in each transfer mode are shown in the following pages. The NT85E500 and the NT85E502 are provided as MEMCs for the NU85E. This section gives examples in the case that the NT85E500 and the NT85E502 are used.
Page 183: Example Of Two-Cycle Single Transfer Timing (Between External Srams Connected To Nt85E500)
Figure 7-30. Example of Two-Cycle Single Transfer Timing (Between External SRAMs Connected to NT85E500) 2-cycle single transfer CPU cycle 2-cycle single transfer Read cycle Write cycle Read cycle Write cycle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output)
Page 184 CHAPTER 7 DMAC Figure 7-31 shows an example of the timing of a 2-cycle single-step transfer (between external SRAMs connected to the NT85E500). The settings of the registers in this figure are as follows. [Register settings] • DBCn register = 0002H (3 transfers) •...
Page 185 Figure 7-31. Example of Two-Cycle Single-Step Transfer Timing (Between External SRAMs Connected to NT85E500) 2-cycle single-step transfer (3 times) VBCLK (Input) VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) VMCTYP2 to VMCTYP0...
Page 186 CHAPTER 7 DMAC Figure 7-32 shows an example of the timing of a 2-cycle line transfer (between the external SRAMs connected to the NT85E500). The settings of the registers in this figure are as follows. [Register settings] • DBCn register = 0007H (8 transfers) •...
Page 187: Example Of Two-Cycle Line Transfer Timing (Between External Srams Connected To Nt85E500)
Figure 7-32. Example of Two-Cycle Line Transfer Timing (Between External SRAMs Connected to NT85E500) 2-cycle line transfer CPU cycle Next line transfer VBCLK (Input) VMTTYP1, VMTTYP0 2H 3H 2H 3H 2H 3H 2H 3H (Output) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output)
Page 188 CHAPTER 7 DMAC Figure 7-33 shows an example of the timing of a 2-cycle block transfer (between the external SRAMs connected to the NT85E500). The settings of the registers in this figure are as follows. [Register settings] • DBCn register = 0006H (7 transfers) •...
Page 189: Example Of Two-Cycle Block Transfer Timing (Between External Srams Connected To Nt85E500)
Figure 7-33. Example of Two-Cycle Block Transfer Timing (Between External SRAMs Connected to NT85E500) 2-cycle block transfer (7 times) VBCLK (Input) VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) VMCTYP2 to VMCTYP0...
Page 190 CHAPTER 7 DMAC Figure 7-34 shows an example of the timing of a 2-cycle single transfer (from RAM connected to the VDB to SDRAM connected to the NT85E502). The settings of the registers in this figure are as follows. [Register settings] •...
Page 191: Example Of Two-Cycle Single Transfer Timing (From Ram Connected To Vdb To Sdram Connected To Nt85E502)
Figure 7-34. Example of Two-Cycle Single Transfer Timing (from RAM Connected to VDB to SDRAM Connected to NT85E502) 2-cycle single transfer CPU cycle 2-cycle single transfer Read cycle Write cycle Read cycle Write cycle VBCLK (Input) SDCLK (Output) Note 1 VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output)
Page 192 CHAPTER 7 DMAC Figure 7-35 shows an example of the timing of a 2-cycle single transfer (from SDRAM connected to the NT85E502 to RAM connected to the VDB). The settings of the registers in this figure are as follows. [Register settings] •...
Page 193: Example Of Two-Cycle Single Transfer Timing (From Sdram Connected To Nt85E502 To Ram Connected To Vdb)
Figure 7-35. Example of Two-Cycle Single Transfer Timing (from SDRAM Connected to NT85E502 to RAM Connected to VDB) 2-cycle single transfer CPU cycle 2-cycle single transfer Read cycle Write cycle Write cycle Read cycle VBCLK (Input) SDCLK (Output) Note 1 VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output)
Page 194 CHAPTER 7 DMAC (2) Flyby transfers Figures 7-36 to 7-41 show examples of the timing of flyby transfers between external SRAM and external I/O connected to the MEMC (NT85E500). The flyby transfer consists of the following states. • T1, T2 states: These are basic states for accessing the NT85E500. •...
Page 195: Example Of Flyby Single Transfer Timing (From External Sram To External I/O Connected To Nt85E500)
Figure 7-36. Example of Flyby Single Transfer Timing (from External SRAM to External I/O Connected to NT85E500) CPU cycle T2 T3 T2 T3 VBCLK (Input) VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0...
Page 196 CHAPTER 7 DMAC Figure 7-37 shows an example of the timing of a flyby single-step transfer (from external SRAM to external I/O connected to the NT85E500). The settings of the registers in this figure are as follows. [Register settings] • DBCn register = 0001H (2 transfers) •...
Page 197: Example Of Flyby Single-Step Transfer Timing (From External Sram To External I/O Connected To Nt85E500)
Figure 7-37. Example of Flyby Single-Step Transfer Timing (from External SRAM to External I/O Connected to NT85E500) CPU cycle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) VMCTYP2 to VMCTYP0...
Page 198 CHAPTER 7 DMAC Figure 7-38 shows an example of the timing of a flyby single-step transfer (from external I/O to external SRAM connected to the NT85E500). The settings of the registers in this figure are as follows. [Register settings] • DBCn register = 0001H (2 transfers) •...
Page 199: Example Of Flyby Single-Step Transfer Timing (From External I/O To External Sram Connected To Nt85E500)
Figure 7-38. Example of Flyby Single-Step Transfer Timing (from External I/O to External SRAM Connected to NT85E500) CPU cycle VBCLK (Input) VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) VMCTYP2 to VMCTYP0...
Page 200 CHAPTER 7 DMAC Figure 7-39 shows an example of the timing of a flyby line transfer (from external SRAM to external I/O connected to the NT85E500). The settings of the registers in this figure are as follows. [Register settings] • DBCn register = 0007H (8 transfers) •...
Page 201: Example Of Flyby Line Transfer Timing (From External Sram To External I/O Connected To Nt85E500)
Figure 7-39. Example of Flyby Line Transfer Timing (from External SRAM to External I/O Connected to NT85E500) Flyby line transfer CPU cycle Flyby line transfer T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3...
Page 202 CHAPTER 7 DMAC Figure 7-40 shows an example of the timing of a flyby block transfer (from external SRAM to external I/O connected to the NT85E500). The settings of the registers in this figure are as follows. [Register settings] • DBCn register = 0007H (8 transfers) •...
Page 203: Example Of Flyby Block Transfer Timing (From External Sram To External I/O Connected To Nt85E500)
Figure 7-40. Example of Flyby Block Transfer Timing (from External SRAM to External I/O Connected to NT85E500) T2 T3 VBCLK (Input) VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) VMCTYP2 to VMCTYP0...
Page 204 CHAPTER 7 DMAC Figure 7-41 shows an example of the timing of a flyby block transfer (from external I/O to external SRAM connected to the NT85E500). The settings of the registers in this figure are as follows. [Register settings] • DBCn register = 0007H (8 transfers) •...
Page 205: Example Of Flyby Block Transfer Timing (From External I/O To External Sram Connected To Nt85E500)
Figure 7-41. Example of Flyby Block Transfer Timing (from External I/O to External SRAM Connected to NT85E500) T2 T3 VBCLK (Input) VMTTYP1, VMTTYP0 (Output) VMA27 to VMA0 (Output) VBDI31 to VBDI0 (Input) VBDO31 to VBDO0 (Output) VMSTZ (Output) VMWRITE (Output) VMBENZ3 to VMBENZ0 (Output) VMCTYP2 to VMCTYP0...
Page 206: Precautions
CHAPTER 7 DMAC 7.15 Precautions (1) Memory boundary Operation is not guaranteed if the address of the transfer source or transfer destination is outside of the area for the DMA object (external memory, RAM, or peripheral macro) during a DMA transfer. (2) Misalign data transfer DMA transfer of misalign data with a 32-bit or 16-bit bus width is not supported.
Page 207 CHAPTER 7 DMAC (4) CPU access during DMA transfer The CPU can access external memory, peripheral macros, or RAM for which no DMA transfer is being performed. The DMAC has a higher VSB bus access right priority than the CPU, so the access from the CPU to the VSB generated during the DMA transfer must wait until the DMA transfer is complete and the bus is available for the CPU.
Page 208: Chapter 8 Intc
CHAPTER 8 INTC The interrupt control unit (INTC), which can process interrupt requests generated for a total of 67 sources, processes various types of interrupt requests from external sources. In addition, exception processing can be started (exception trap) due to a TRAP instruction (software exception) or due to the generation of an exception event (fetching of an illegal opcode).
Page 209 CHAPTER 8 INTC Table 8-1. Interrupt/Exception List (2/3) Type Classifi- Interrupt/Exception Source Default Exception Handler Restored cation Priority Code Address Name Control Register Generating Source Maskable Interrupt INT7 PIC7 INT7 input 00F0H 000000F0H nextPC Interrupt INT8 PIC8 INT8 input 0100H 00000100H nextPC Interrupt...
Page 210 CHAPTER 8 INTC Table 8-1. Interrupt/Exception List (3/3) Type Classifi- Interrupt/Exception Source Default Exception Handler Restored cation Priority Code Address Name Control Register Generating Source Maskable Interrupt INT44 PIC44 INT44 input 0340H 00000340H nextPC Interrupt INT45 PIC45 INT45 input 0350H 00000350H nextPC Interrupt...
Page 211: Non-Maskable Interrupts (Nmi)
CHAPTER 8 INTC 8.2 Non-Maskable Interrupts (NMI) A non-maskable interrupt request (NMI) is acknowledged unconditionally even if the NU85E is in an interrupt disabled (DI) state. A non-maskable interrupt request is generated according to DCNMIn pin input (n = 2 to 0). When a rising edge is input to the DCNMIn pin, a non-maskable interrupt (NMIn) is generated.
Page 212: Example Of Non-Maskable Interrupt Request Acknowledgement Operation
CHAPTER 8 INTC Figure 8-1. Example of Non-Maskable Interrupt Request Acknowledgement Operation (1/2) (a) Multiple NMI requests generated at the same time • NMI0 and NMI1 requests generated • NMI0 and NMI2 requests generated simultaneously simultaneously Main routine Main routine NMI2 servicing NMI1 servicing NMI0 and NMI2...
Page 213 CHAPTER 8 INTC Figure 8-1. Example of Non-Maskable Interrupt Request Acknowledgement Operation (2/2) (b) NMI request generated during NMI servicing NMI being NMI request generated during NMI servicing serviced NMI0 NMI1 NMI2 • NMI0 request generated • NMI1 request generated •...
Page 214: Operation
CHAPTER 8 INTC 8.2.1 Operation If a non-maskable interrupt is generated according to DCNMIn input, the CPU performs the following processing and shifts control to the handler routine (n = 2 to 0). <1> Save the restored PC in the FEPC. <2>...
Page 215: Restore
CHAPTER 8 INTC 8.2.2 Restore (1) NMI0 Control is returned from NMI0 servicing according to the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and shifts control to the restored PC address. <1> Since the EP bit of the PSW is 0 and the NP bit is 1, fetch the restored PC and PSW from the FEPC and FEPSW.
Page 216: Maskable Interrupts
CHAPTER 8 INTC 8.3 Maskable Interrupts A maskable interrupt request is an interrupt request for which the acknowledgement of the interrupt can be masked according to the interrupt control register. There are 64 interrupt sources for maskable interrupts. A maskable interrupt request is generated according to INTn pin input (n = 63 to 0). When a rising edge is input to the INTn pin, a maskable interrupt (INTn) is generated.
Page 217: Maskable Interrupt Processing Format
CHAPTER 8 INTC Figure 8-4. Maskable Interrupt Processing Format INTn input INTC acknowledgement Interrupt request? Interrupt unmasked? Priority higher than that of interrupt currently processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with same priority? Maskable interrupt request Interrupt request pending CPU processing...
Page 218: Restore
CHAPTER 8 INTC 8.3.2 Restore Control is returned from maskable interrupt service according to the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and shifts control to the restored PC address. <1> Since the EP bit of the PSW is 0 and the NP bit is 0, fetch the restored PC and PSW from the EIPC and EIPSW.
Page 219: Maskable Interrupt Priorities
CHAPTER 8 INTC 8.3.3 Maskable interrupt priorities The INTC provides multiple interrupt service that acknowledges another interrupt while an interrupt is being serviced. Multiple interrupts can be controlled according to priorities. Priority control includes control according to default priorities and programmable priority control according to the interrupt control register (PICn).
Page 220: Servicing Example In Which Another Interrupt Request Is Issued During Interrupt Servicing
CHAPTER 8 INTC Figure 8-6. Servicing Example in Which Another Interrupt Request Is Issued During Interrupt Servicing (1/2) Main routine Servicing of <a> Servicing of Interrupt request<a> Interrupt request Interrupt request is acknowledged because → → (level 3) (level 2) the priority of ...
Page 221 CHAPTER 8 INTC Figure 8-6. Servicing Example in Which Another Interrupt Request Is Issued During Interrupt Servicing (2/2) Main routine Servicing of Interrupt request<j> Servicing of <k> → (level 3) Interrupt request<k> Interrupt request <j> is held pending because →...
Page 222: Servicing Example For Simultaneously Issued Interrupt Requests
CHAPTER 8 INTC Figure 8-7. Servicing Example for Simultaneously Issued Interrupt Requests Main routine Servicing of Interrupt requests and <c> are acknowledged first according to their priorities. Because the priorities of and <c> are the same, is acknowledged first because it Interrupt request <a>...
Page 223: Control Registers
CHAPTER 8 INTC 8.3.4 Control registers (1) Interrupt control registers 0 to 63 (PIC0 to PIC63) The interrupt control registers, which are assigned to each interrupt request (maskable interrupt), set control conditions for each interrupt. These registers can be read or written in 8-bit or 1-bit units. Figure 8-8.
Page 224: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
CHAPTER 8 INTC (2) Interrupt mask registers 0 to 3 (IMR0 to IMR3) The interrupt mask registers maintain the mask status of each maskable interrupt. The PMKn bit of this register and the PMKn bit of the PICn register are linked (n = 0 to 63). The IMRm register can be read or written in 16-bit units (m = 0 to 3).
Page 225: In-Service Priority Register (Ispr)
CHAPTER 8 INTC (3) In-service priority register (ISPR) This register maintains the priority level of the maskable interrupt that is being acknowledged. When an interrupt request is acknowledged, the bit corresponding to the priority level of that interrupt request is set (1) and maintained while the interrupt is being serviced.
Page 226: Maskable Interrupt Status Flag (Id)
CHAPTER 8 INTC 8.3.5 Maskable interrupt status flag (ID) This flag, which controls the operation status of maskable interrupts, stores information indicating whether the acknowledgement of interrupt requests is enabled or disabled. It is assigned to bit 5 of the program status word (PSW). Figure 8-11.
Page 227: Software Exception
CHAPTER 8 INTC 8.4 Software Exception A software exception, which is an exception that is generated when the CPU executes the TRAP instruction, can always be acknowledged. 8.4.1 Operation If a software exception is generated, the CPU performs the following processing and shifts control to the handler routine.
Page 228: Restore
CHAPTER 8 INTC 8.4.2 Restore Control is returned from software exception processing according to the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and shifts control to the restored PC address. <1> Since the EP bit of the PSW is 1, fetch the restored PC and PSW from the EIPC and EIPSW. <2>...
Page 229: Exception Trap
The exception trap is an interrupt that is requested when the illegal execution of an instruction occurs. In the NU85E, the illegal opcode exception (ILGOP: Illegal opcode trap) is assigned for the exception trap. An illegal opcode exception is generated when the sub-opcode of the instruction to be executed next is an illegal opcode.
Page 230: Operation
CHAPTER 8 INTC 8.5.2 Operation If an exception trap is generated, the CPU performs the following processing and shifts control to the handler routine. <1> Save the restored PC in the DBPC. <2> Save the current PSW in the DBPSW. <3>...
Page 231: Interrupt Response Time
CHAPTER 8 INTC 8.6 Interrupt Response Time Except in the following cases, the interrupt response time is a minimum of 5 clocks. To input interrupt requests continuously, leave a space of at least 5 clocks between interrupt request inputs. • During software or hardware STOP mode •...
Page 232: Chapter 9 Test Function
When a low-level signal is being input to the BUNRI pin, the pins other than the test pins are enabled, and the NU85E is in normal mode. At this time, input to the TBI39 to TBI0 pins is ignored, and the TBO34 to TBO0 pins are set to high impedance.
Page 233: Bunriout Pin
When a high-level signal is being input to the BUNRI pin and a low-level signal is being input to the TEST pin, the NU85E is in standby test mode. The input to the TBI39 to TBI0 pins is ignored, and the TBO34 to TBO0 pins are set to high impedance.
Page 234: Example Of Connection Of Peripheral Macro In Test Mode
The NPB peripheral macro, MEMC (NT85E500, NT85E502), instruction cache, and data cache supported by NEC are tested via the NU85E. An example of the connections between the NU85E, the NPB peripheral macro, and the MEMC is shown below. Figure 9-1. Peripheral Macro Connection Example...
Page 235: Handling Of Each Pin In Test Mode
Remark n = 1, 0 (3) Precautions when NB85E901 is connected When the NB85E901 (RCU) is connected to the NU85E, the following pins are used in the unit test mode. All of these pins should be attached off chip as external pins.
Page 236: Chapter 10 Nb85E901
The NB85E901 (RCU: Run Control Unit) is a run control unit that realizes the execution of JTAG communication and debug processing. Connection of the NB85E901 with an N-Wire type in-circuit emulator (N-Wire type IE) makes it possible to perform on-chip debugging on the NU85E. 10.1 Symbol Diagram...
Page 237: Pin Functions
Input Wait request input ROMTYPE Input NEC reserved pin (input low level) DCOP13 to DCOP0 Output NEC reserved pin (leave open) NU85E connection pins VBCLK Input System clock input DBI5 to DBI0 Output Debug control output DBO14 to DBO0 Input...
Page 238: Pin Functions
CHAPTER 10 NB85E901 10.2.2 Pin functions (1) N-Wire type IE connection pins Caution N-Wire type IE connection pins (DCK, DRSTZ, DMS, DDI, DDO, DBINT) must be attached off the chip as external pins since they are used in the unit test mode of the NB85E901. Do not use these pins as alternate function pins (however, the DBINT pin can be used as the alternate function of a pin other than the TBI39 to TBI0, TBO34 to TBO0, TEST, BUNRI, DCK, DRSTZ, DMS, DDI, and DDO pins).
Page 239 This is the reset output pin. Connect it to the DCRESZ pin on the NU85E. (h) DCSTOPZ (output) This is the hardware STOP mode request output pin. Connect it to the DCSTOPZ pin on the NU85E. DCNMI2 to DCNMI0 (output) These are non-maskable interrupt output pins.
Page 240 (5) Test mode pins (a) BUNRI (input) This is the input pin for selecting normal mode or test mode. (b) TEST (input) This is the test bus control input pin. Connect it to the TMODE1 pin on the NU85E. Preliminary User’s Manual A14874EJ3V0UM...
Page 241: Recommended Connection Of Unused Pins
Input a high level. NMI2 to NMI0, VAREQ, ROMTYPE Input Input a low level. DCOP13 to DCOP0 Output Leave open. − NU85E connection pins VBCLK, DBO14 to DBO0, TMODE1, Input VBTCLK − DBI5 to DBI0 Output − DBB15 to DBB0...
Page 242: Pin Status
CHAPTER 10 NB85E901 10.2.4 Pin status The following table shows the status in each operating mode of the pins that have output functions. Table 10-1. Pin Status in Each Operating Mode Pin Name Pin Status Note Reset Software Hardware HALT Mode Standby Unit Test STOP Mode...
Page 243 CHAPTER 10 NB85E901 Caution The following input pins must be set according to the table below in the respective operating modes. Pin Name Pin Status Note Reset Software Hardware HALT Mode Standby Unit Test STOP Mode STOP Mode Test Mode Mode DRSTZ H/Operates...
Page 244: Debug Function
(2) On-chip debug By connecting with the N-Wire type IE, it is possible to debug the NB85E901 on the NU85E chip. For details on the above connection, refer to 10.5 N-Wire Type IE Connection. (3) Forcible reset function The NB85E901 unit can be forcibly reset.
Page 245: Nu85E Connection Example
CHAPTER 10 NB85E901 10.4 NU85E Connection Example Figure 10-1 shows an example of the connection between the NB85E901 and the NU85E. Figure 10-1. NB85E901 and NU85E Connection Example Clock NB85E901 (RCU) generator (CG) DRSTZ VBCLK Connection with N-Wire type in-circuit emulator...
Page 246: N-Wire Type Ie Connection
CHAPTER 10 NB85E901 10.5 N-Wire Type IE Connection In order to connect the N-Wire type IE (IE-70000-MC-NW-A), it is necessary to mount a connector for IE connection and a connection circuit on the target system. Figure 10-2. N-Wire Type IE Connection Connector for IE connection (8830E-026-170S/L) (product of KEL Corporation) To host machine...
Page 247 CHAPTER 10 NB85E901 Table 10-2. IE Connector Pin Functions (Target System Side) Pin No. Pin Name Pin Function TRCCLK Input Trace clock input TRCDATA0 Input Trace data 0 input TRCDATA1 Input Trace data 1 input TRCDATA2 Input Trace data 2 input TRCDATA3 Input Trace data 3 input...
Page 248: Example Of Recommended Circuit When Connecting Nb85E901 And Nu85E
10.5.2 Example of recommended circuit when connecting NB85E901 and NU85E Figure 10-4 shows an example of the circuit recommended for IE connector section (target system side). Figure 10-4. Example of Recommended Circuit for IE Connection (NU85E + NB85E901) IE connector...
Page 249: Appendix A Rom/Ram Access Timing
APPENDIX A ROM/RAM ACCESS TIMING Figure A-1. ROM Access Timing VBCLK (Input) IROMEN (Output) IROMA19 to IROMA2 Hold (Output) IROMZ31 to IROMZ0 Note (Input) Note Data should be retained from when the IROMEN output becomes high level until the VBCLK signal rises. Remarks 1.
Page 250: Ram Access Timing
APPENDIX A ROM/RAM ACCESS TIMING Figure A-2. RAM Access Timing (a) Read timing VBCLK (Input) IRAMRWB (Output) IRAMEN (Output) IRAMA27 to IRAMA2 (Output) IRAMZ31 to IRAMZ0 (Input) Remarks 1. Ax: Arbitrary address Dx: Data corresponding to address “Ax” : RAM data sampling timing (b) Write timing VBCLK (Input) IRAMRWB (Output)
Page 251: Appendix B Index
APPENDIX B INDEX DA27 to DA16 ............154 DAD1, DAD0 ............158 Address space ............58 DADC0 to DADC3 ..........157 Application system example ........18 Data area ..............60 Data transfer using VSB...........94 DBB15 to DBB0............41 BBR ............... 118 DBC0 to DBC3 ............156 BC15 to BC0............
Page 252 APPENDIX B INDEX Endian configuration register ........87 IDDRRQ ..............39 Endian setting function..........87 IDDWRQ..............39 ENn ................ 160 IDEA27 to IDEA0............40 EP ................57 IDED31 to IDED0 .............40 EVAD15 to EVAD0........... 41 IDES .................40 EVASTB ..............41 IDHUM..............40 EVCLRIP..............41 IDMASTP..............36 EVDSTB..............
Page 253 Programmable peripheral I/O area......120 Programmable peripheral I/O area selection function..............83 NB85E901 ............. 234 PSC ................137 NB85E901 and NU85E connection example ..243 PSW ..............55, 57 Next address setting function ........ 162 NMI ................ 209 NMI0M ..............137 r0 to r31..............53 NMI1M ..............
Page 254 APPENDIX B INDEX SA15 to SA0 ............153 Two-cycle transfer ..........173 SA27 to SA16 ............152 SAD1, SAD0 ............158 Unit test mode ............231 SAT ................57 Single transfer mode..........166 Single-step transfer mode........168 VAACK ..............30 Software exception ..........225 VAPREQ..............30 Software STOP mode ..........
Page 255 APPENDIX B INDEX VSLOCK ..............31 VSSELPZ..............33 Wait insertion function..........123 VSSTZ ..............30 VSWAIT ..............33 VSWC ..............123 Z ................57 VSWL2 to VSWL0 ..........124 VSWRITE ..............31 Preliminary User’s Manual A14874EJ3V0UM...
Page 256: Appendix C Revision History
Modification of 9.1.3 BUNRIOUT pin p.232 Modification of Figure 9-1 Peripheral Macro Connection Example p.233 Modification of 9.4 (2) Test mode pins p.238 Modification of 10.2.2 (5) TEST p.240 Modification of Figure 10-1 NB85E901 and NU85E Connection Example Preliminary User’s Manual A14874EJ3V0UM...
Page 257 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

This manual is also suitable for:

Nu85ea

Renesas NU85E Preliminary User's Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu

Chapter 4 Bcu

Chapter 5 Bbr

Chapter 6 Stbc

Chapter 7 Dmac

Chapter 8 Intc

Chapter 9 Test Function

Chapter 10 Nb85E901

Appendix A Rom/Ram Access Timing

Appendix B Index

Appendix C Revision History

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