Npb Read/Write Timing; Halfword Access Timing - Renesas NU85E Preliminary User's Manual

5.4 NPB Read/Write Timing

Figure 5-8 to Figure 5-13 show the basic read/write timing of NPB, Figure 5-14 shows a timing example for
read/write access to a bus slave connected to the NU85E and NPB, and Figure 5-15 shows a timing example of write
access to a peripheral I/O register. Each one of these figures shows the timing as seen from the NU85E when the
NU85E has the bus access right.
Remark O mark: Sampling timing
A.x: Arbitrary address output from the VPA13 to VPA0 pins
D.x: I/O data for address "A.x"
: Signal in undefined state (for output signal), arbitrary level (for input signal)
VPA13 to VPA0
(Output)
VPDO15 to VPDO0
(Output)
VPDI15 to VPDI0
(Input)
VPWRITE (Output)
VPSTB (Output)
VPUBENZ (Output)
VPLOCK (Output)
VPRETR (Input) L
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CHAPTER 5 BBR
Figure 5-8. Halfword Access Timing
Write cycle
A.0
D.0
Preliminary User's Manual A14874EJ3V0UM
Read cycle
A.1
D.1