Renesas NU85E Preliminary User's Manual page 192

Figure 7-35 shows an example of the timing of a 2-cycle single transfer (from SDRAM connected to the
NT85E502 to RAM connected to the VDB). The settings of the registers in this figure are as follows.
[Register settings]
• DBCn register = 0001H (2 transfers)
• SCRn register Note
= 2062H (CAS latency = 2,
Note An NT85E502 register.
190
CHAPTER 7 DMAC
number of wait states = 1,
address shift width = 2 bits (32-bit data bus),
low address width = 11 bits,
address multiplexed width = 10 bits)
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