Renesas NU85E Preliminary User's Manual page 42

(a) IDDRRQ (input)
This is the pin to which VSB read operation requests are input from the data cache.
(b) IDDWRQ (input)
This is the pin to which VSB write operation requests are input from the data cache.
(c) IDSEQ4, IDSEQ2 (input)
These are the pins to which the read/write operation type settings are input from the data cache.
(4) IRRSA (output)
This is the pin from which the VDB hold status is output to the data cache.
An active level (high level) is output when the VDB is accessing RAM or is in the hold state.
(5) IDRETR (output)
This is the pin from which read retry requests are output to the data cache.
(6) IDUNCH (output)
This is the pin from which the uncache status is output to the data cache.
A low level is output when the area in which the data cache setting has been set to cache-enable using the
cache configuration register (BHC) is accessed.
(7) IDDRDY (output)
This is the pin from which read data ready signals are output to the data cache.
Upon a data cache miss-hit, when the NU85E has finished fetching the data to be read from the external
memory, this signal is output to indicate that a refill for the data cache is ready.
(8) IDRRDY (input)
This is the pin to which read data ready signals are input from the data cache.
(9) IDHUM (input)
This is the pin to which hit-under-miss-hit read signals are input from the data cache.
A high level is input in cases when a subsequent access is made to the data cache while the external memory is
being accessed due to the generation of a miss-hit during a read operation, and the data that scored a hit on this
subsequent access is input to the NU85E ahead of the data from the external memory (hit-under-miss-hit).
(10) IDEA27 to IDEA0 (input)
These pins constitute a bus to which addresses are input from the data cache.
The address to be accessed is input to the NU85E upon a data cache miss-hit.
(11) IDED31 to IDED0 (input/output)
These pins constitute a data bus through which data is input/output from/to the data cache.
Data for refilling the data cache and data written to the external memory in write back mode is exchanged.
(12) IDES (output)
This is an NEC reserved pin. When using the data cache, be sure to connect this pin to the IDES pin of the
connected data cache. When not using the data cache, leave this pin open.
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CHAPTER 2 PIN FUNCTIONS
Preliminary User's Manual A14874EJ3V0UM