Reset Timing; Reset Timing - Renesas NU85E Preliminary User's Manual

4.9.5 Reset timing

The reset timing of when a low level is input to the IFIROME pin (the connected ROM is used as external memory
(via the VSB)) is shown below.
Caution Be sure to input the VBCLK signal continuously during the reset period (the period when
DCRESZ is low level).
VBCLK (Input)
DCRESZ (Input)
VMTTYP1, VMTTYP0
(0, 0)
(Output)
VMLOCK (Output) L
VMA27 to VMA0 (Output)
VMWRITE (Output) L
VMBENZ3 to VMBENZ0
(Output)
VMCTYP2 to VMCTYP0
(Output)
VMSEQ2 to VMSEQ0
(Output)
VMSIZE1, VMSIZE0
(Output)
VMSTZ (Output)
VDCSZ7 to VDCSZ0
(Output)
VDSELPZ (Output) H
VBDI31 to VBDI0 (Input)
VBDO31 to VBDO0
L
(Output)
IFIROME (Input) L
Remarks 1. O mark: Sampling timing
A.x:
D.x:
:
2. The timing seen from the NU85E when the NU85E has the bus access right is shown.
CHAPTER 4 BCU
Figure 4-16. Reset Timing
(1,0)
(0,0,0,0)
FEH
Arbitrary address output from the VMA27 to VMA0 pins
Input data from address "A.x"
Arbitrary input level
Preliminary User's Manual A14874EJ3V0UM
(0, 0)
(1,1,1,1)
Undefined
FFH
(1, 0) (0, 0) (1, 0)
A.0 A.1 A.2
(0,0,0,0) (1,1,1,1) (0,0,0,0)
(1,0,0) (0,0,0) (1,0,0)
(0,0,0)
(1, 0)
FEH FFH FEH
D.0 D.1
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