Dma Transfer Timing Examples - Renesas NU85E Preliminary User's Manual

7.14 DMA Transfer Timing Examples

Examples of the DMA transfer timing in each transfer mode are shown in the following pages.
The NT85E500 and the NT85E502 are provided as MEMCs for the NU85E. This section gives examples in the
case that the NT85E500 and the NT85E502 are used.
(1) Two-cycle transfer
Figures 7-30 to 7-33 show examples of the timing of 2-cycle transfers between external SRAMs connected to
the MEMC (NT85E500). Figures 7-34 and 7-35 show examples of the timing of 2-cycle transfers between RAM
connected to the VDB and SDRAM connected to the MEMC (NT85E502).
Remarks 1. The levels of the broken-line portions of the VMCTYP2 to VMCTYP0, VMSEQ2 to VMSEQ0,
VMSIZE1, VMSIZE0, and DI31 to DI0 signals indicate the undefined state.
2. The O marks indicate the sampling timing.
3. n = 3 to 0
Figure 7-30 shows an example of the timing of a 2-cycle single transfer (between external SRAMs connected to
the NT85E500). The settings of the registers in this figure are as follows.
[Register settings]
• DBCn register = 0001H (2 transfers)
• ASC register
Note
= 0000H (No address setting wait states)
• BCC register
Note
= 0000H (No idle states)
• DWC0 register Note
= 7377H (CS2 wait states = 3)
Note An NT85E500 register.
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CHAPTER 7 DMAC
Preliminary User's Manual A14874EJ3V0UM