Maskable Interrupts; Operation - Renesas NU85E Preliminary User's Manual

8.3 Maskable Interrupts

A maskable interrupt request is an interrupt request for which the acknowledgement of the interrupt can be
masked according to the interrupt control register. There are 64 interrupt sources for maskable interrupts.
A maskable interrupt request is generated according to INTn pin input (n = 63 to 0). When a rising edge is input to
the INTn pin, a maskable interrupt (INTn) is generated.
If multiple maskable interrupt requests are generated at the same time, their priorities are determined according to
the default priorities. In addition to the default priority, eight interrupt priority levels can be set according to the
interrupt control register (programmable priority control).
When an interrupt request is acknowledged, interrupt disabled (DI) state is set, and the acknowledgement of
subsequent maskable interrupt requests is disabled.
If the EI instruction is executed during an interrupt service routine, interrupt enabled (EI) state is set, and the
acknowledgement of interrupt requests having higher priorities than the priority level of the currently acknowledged
interrupt request (specified by the interrupt control register) is enabled. Interrupts having the same priority level
cannot be nested.
However, the following processing is required for multiple interrupt service.
<1> Save the EIPC and EIPSW in memory or general-purpose registers before executing the EI instruction.
<2> Before executing the RETI instruction, execute the DI instruction and return the values that were saved in
step <1> to the EIPC and EIPSW.

8.3.1 Operation

If a maskable interrupt is generated according to INTn input, the CPU performs the following processing and shifts
control to the handler routine.
<1> Save the restored PC in the EIPC.
<2> Save the current PSW in the EIPSW.
<3> Write the exception code in the lower halfword (EICC) of the ECR.
<4> Set the ID bit of the PSW and clear the EP bit.
<5> Set the handler address for the interrupt in the PC and shift control.
An INTn input that is masked by the INTC and an INTn input that was generated while another interrupt was being
serviced (PSW.NP = 1 or PSW.ID = 1) are kept pending within the INTC. In this case, if the mask is canceled or the
RETI and LDSR instructions are used to set PSW.NP to 0 and PSW.ID to 0, the new maskable interrupt service is
started according to the INTn input that had been pending.
Figure 8-4 shows the processing format of maskable interrupt service.
214
CHAPTER 8 INTC
Preliminary User's Manual A14874EJ3V0UM