Renesas NU85E Preliminary User's Manual page 99

(6) Transfer response
The transfer response is indicated by the VMWAIT, VMAHLD, and VMLAST signals, which are output from the
bus slave (The signal names on the bus slave side are VSWAIT, VSAHLD, and VSLAST). These signals
become effective only while the VBCLK signal is low level.
VMWAIT VMAHLD
0
0
1
1
Other than the above
Remark 0: low-level 1: high-level
Caution Once the VMAHLD signal becomes active (1), hold the active level (1) until the VMWAIT signal
becomes inactive (0).
It is not possible to return to the wait state from the address hold state during a bus cycle.
VMWAIT
VMAHLD
(7) Transfer direction
The bus master uses the VMWRITE signal to indicate the transfer direction. This signal outputs a high level
during write access.
(8) Data bus direction control
The VBDC signal is the data input (VBDI31 to VBDI0) control signal output pin. This signal outputs a high level
during read access.
The VBDV signal is the data output (VBDO31 to VBDO0) control signal output pin. This signal outputs a high
level during write access.
Remark 0: low-level 1: high-level
CHAPTER 4 BCU
Table 4-6. VMWAIT, VMAHLD, and VMLAST Signals
VMLAST
0 0 Status when the current transfer is completed (ready status)
0 1 Last response (burst transfer last response status)
0 0 Wait response (wait status)
1 0 Maintains address and control signal (address hold status)
(Reserved for future function expansion)
Table 4-7. VBDC and VBDV Signals
VBDC VBDV
0 1 Read access
1 0 Write access
Preliminary User's Manual A14874EJ3V0UM
Explanation
VMWAIT
VMAHLD
Explanation
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