In-Service Priority Register (Ispr) - Renesas NU85E Preliminary User's Manual

(3) In-service priority register (ISPR)

This register maintains the priority level of the maskable interrupt that is being acknowledged. When an interrupt
request is acknowledged, the bit corresponding to the priority level of that interrupt request is set (1) and
maintained while the interrupt is being serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority
among the bits that are set (1) within the ISPR register is automatically cleared (0). However, it is not cleared (0)
when control returns from non-maskable interrupt service or exception processing.
This register is read-only in 8-bit or 1-bit units.
7 6
ISPR ISPR7 ISPR6
Bit position Bit name
7 to 0 ISPR7 to
ISPR0
Remark n = 7 to 0 (priority levels)
CHAPTER 8 INTC
Figure 8-10. In-Service Priority Register (ISPR)
5 4
ISPR5 ISPR4 ISPR3
Indicates the priority of the interrupt that is being acknowledged.
0: Interrupt request having priority n has not been acknowledged
1: Interrupt request having priority n is being acknowledged
Preliminary User's Manual A14874EJ3V0UM
3 2 1
ISPR2 ISPR1
Function
0
Address After reset
ISPR0
FFFFF1FAH 00H
223