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Figure 5-14. Read/Write Timing of Bus Slave Connected to NPB (2/4)
(b) Example of timing of halfword-data write to NPB peripheral macro (programmable peripheral I/O area)
VBCLK (Input)
VMTTYP1, VMTTYP0 (Output)
(1,0)
VMLOCK (Output)
L
VMA27 to VMA0 (Output)
VMWRITE (Output)
VMBENZ3 to VMBENZ0 (Output)
VMCTYP2 to VMCTYP0 (Output)
VMSEQ2 to VMSEQ0 (Output)
VMSIZE1, VMSIZE0 (Output)
VMSTZ (Output)
VDCSZ7 to VDCSZ0 (Output)
VDSELPZ (Output)
VBDI31 to VBDI0 (Input)
L
VBDO31 to VBDO0 (Output)
VSWAIT (Output)
VSAHLD (Output)
VSLAST (Output)
VMWAIT (Input)
VMAHLD (Input)
L
VMLAST (Input)
VPA13 to VPA0 (Output)
VPDI15 to VPDI0 (Input)
VPDO15 to VPDO0 (Output)
VPSTB (Output)
VPRETR (Input)
L
VPWRITE (Output)
VPUBENZ (Output)
L
(1,1)
(1,0)
2403804H
(1,1,0,0)
(0,0,1)
(0,0,0)
(0,1)
FFH
xxxx00FFH
3804H
00FFH
(1,1)
2403806H
xxxx55AAH
3806H
55AAH
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