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(2) Clock control when setting or canceling hardware STOP mode
(a) When setting hardware STOP mode
<1> Input the active level (low level) of the DCSTOPZ signal.
<2> Set the STOP mode request signal (STPRQ) to active (high level) and output it to the memory
controller.
<3> Input the active level (high level) of the acknowledge signal (STPAK) from the memory controller that
received the STPRQ signal.
<4> Set the hardware STOP mode request signal (HWSTOPRQ) to active (high level) and output it to the
clock control circuit (Use this HWSTOPRQ signal to stop the VBCLK output from the clock control
circuit).
(b) When canceling hardware STOP mode
<1> Input the DCRESZ signal or the inactive level (high level) of the DCSTOPZ signal.
<2> Set the hardware STOP mode request signal (HWSTOPRQ) to inactive (low level) and output it to the
clock control circuit (clock generator starts operation).
<3> After the oscillation stabilization time, input the active level (high level) of the CGREL signal from the
clock control circuits simultaneous with the VBCLK signal (The input of the VBCLK signal returns the
STPRQ and STPAK outputs to low level).
Caution Input an active level (high level) to the CGREL pin for one clock or more.
When setting the hardware STOP mode again, be sure to input an inactive level (low level)
to the CGREL pin before setting.
Remark
A level latch is used for the DCRESZ signal, which can therefore be input asynchronously to
VBCLK.
CHAPTER 6 STBC
Preliminary User's Manual A14874EJ3V0UM
147
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