Line Transfer Mode; Line Transfer Example 1; Line Transfer Example 2 - Renesas NU85E Preliminary User's Manual

7.8.3 Line transfer mode

In line transfer mode, the DMAC releases the bus after every four byte, halfword, or word transfers. If there is a
subsequent DMA transfer request, four transfers are performed again. This operation continues until a terminal count
occurs. In 2-cycle transfer, the operation from read to write is repeated four times.
If a higher priority DMA transfer request is generated while the DMAC has released the bus, the higher priority DMA
transfer request always takes precedence. However, if a lower priority DMA transfer request is generated within one
clock after the end of a line transfer, even if the previous higher priority DMA transfer request signal stays active, this
request is not prioritized, and the next DMA transfer after the bus is released for the CPU is a transfer based on the
newly generated, lower priority DMA transfer request.
Figures 7-18 to 7-21 show examples for line transfer.
DMARQ3
(Input)
CPU DMA3 DMA3 DMA3 DMA3
Note The bus is always released.
Figure 7-19 shows a line transfer mode example in which a higher priority DMA transfer request is generated.
DMA channels 0 to 2 are used for a block transfer, and channel 3 is used for a line transfer.
DMARQ0
(Input)
DMARQ1
(Input)
DMARQ2
(Input)
DMARQ3
(Input)
CPU CPU DMA3 DMA3
Note The bus is always released.
CHAPTER 7 DMAC
Figure 7-18. Line Transfer Example 1
Note
CPU DMA3 DMA3 DMA3
Figure 7-19. Line Transfer Example 2
Note Note
DMA3 DMA3 CPU DMA0 DMA0 CPU DMA1
DMA channel 0
terminal count
Preliminary User's Manual A14874EJ3V0UM
Note
DMA3 CPU CPU CPU DMA3
Note Note
DMA1 CPU DMA2 DMA2 CPU DMA3
DMA channel 1
terminal count
DMA channel 2
terminal count
DMA3 DMA3 DMA3 CPU CPU
DMA channel 3
terminal count
Note
DMA3 DMA3 DMA3 CPU CPU
DMA channel 3
terminal count
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