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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BPC
1
0
0
[64 MB mode]
3FFFFFFH
Bank 15
3E00000H
3DFFFFFH
Bank 14
3C00000H
3BFFFFFH
Bank 13
3A00000H
39FFFFFH
Bank 12
3800000H
37FFFFFH
Bank 11
3400000H
33FFFFFH
Bank 10
3000000H
2FFFFFFH
Bank 9
2800000H
27FFFFFH
Bank 8
2000000H
1FFFFFFH
Bank 7
1800000H
17FFFFFH
Bank 6
1000000H
0FFFFFFH
Bank 5
0C00000H
0BFFFFFH
Bank 4
0800000H
07FFFFFH
Bank 3
0600000H
05FFFFFH
Bank 2
0400000H
03FFFFFH
Bank 1
0200000H
01FFFFFH
Bank 0
0000000H
122
CHAPTER 5 BBR
Figure 5-5. BPC Register Setting Example
(a) BPC register setting
0 1 0 0 1 0 0 0 0 0
(b) Memory map
2402FFFH
Programmable peripheral
I/O area
2400000H
Preliminary User's Manual A14874EJ3V0UM
0
0
0
Programmable peripheral I/O area
starting address: 2400000H
Programmable peripheral I/O area:
Can be accessed
[256 MB mode]
FFFFFFFH
Bank 15
FE00000H
FDFFFFFH
Bank 14
FC00000H
FBFFFFFH
Bank 13
FA00000H
F9FFFFFH
Area 3
Bank 12
F800000H
F7FFFFFH
C000000H
BFFFFFFH
Area 2
8000000H
7FFFFFFH
Area 1
4000000H
3FFFFFFH
0800000H
07FFFFFH
Bank 3
Area 0
0600000H
05FFFFFH
Bank 2
0400000H
03FFFFFH
Bank 1
0200000H
01FFFFFH
Bank 0
0000000H
2402FFFH
Programmable peripheral
I/O area
2400000H
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