Forcible Interruption; Dma Transfer Forcible Interruption Example - Renesas NU85E Preliminary User's Manual

7.12 Forcible Interruption

DMA transfer can be forcibly interrupted by inputting the IDMASTP signal during the DMA transfer.
At this time, the DMAC clears (0) the ENn bit of the DCHCn register of all channels to set the state in which DMA
transfer is disabled, completes the DMA transfer that was being executed when the IDMASTP signal was input, and
the bus releases to the CPU (n = 0 to 3).
For single-step transfer mode, block transfer mode, or line transfer mode, the DMA transfer request is maintained
in the DMAC. When the ENn bit is set (1), the DMA transfer is restarted from the point at which the DMA transfer was
interrupted.
For single transfer mode, when the ENn bit is set (1), the next DMA transfer request is acknowledged and DMA
transfer begins.
Caution To forcibly interrupt DMA transfer and stop the next transfer from occurring, the IDMASTP signal
must be made active before the end of the DMA transfer currently under execution. Moreover,
although it is possible to restart DMA transfer following an interruption, this transfer cannot be
executed under new settings (new conditions). Execute DMA transfer under new settings either
after the end of the current transfer or after transfer has been forcibly terminated by setting the
INITn bit of the DCHCn register (n = 0 to 3).
IDMASTP (Input)
DDIS register
DRST register
EN0 bit of
DCHC register
CHAPTER 7 DMAC
Figure 7-28. DMA Transfer Forcible Interruption Example
Forcible
interruption
DMA transfer
DMA transfer
suspended
Preliminary User's Manual A14874EJ3V0UM
Forcible
Transfer restart
interruption
DMA transfer DMA transfer suspended
01H
01H
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