Renesas NU85E Preliminary User's Manual page 13

7.4 DMA Channel Priorities ........................................................................................................................... 151
7.5 Control Registers..................................................................................................................................... 152
7.5.1 DMA source address registers 0 to 3 (DSA0 to DSA3) ...............................................................152
7.5.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) ........................................................154
7.5.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)..................................................................156
7.5.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) .....................................................157
7.5.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)..........................................................159
7.5.6 DMA disable status register (DDIS) .............................................................................................160
7.5.7 DMA restart register (DRST)........................................................................................................161
7.6 Next Address Setting Function .............................................................................................................. 162
7.7 DMA Bus State ......................................................................................................................................... 163
7.7.1 Bus state types ............................................................................................................................163
7.7.2 DMAC bus cycle state transitions ................................................................................................165
7.8 Transfer Modes ........................................................................................................................................ 166
7.8.1 Single transfer mode....................................................................................................................166
7.8.2 Single-step transfer mode............................................................................................................168
7.8.3 Line transfer mode.......................................................................................................................169
7.8.4 Block transfer mode.....................................................................................................................171
7.8.5 One-time transfer when executing single transfers using DMARQn signal .................................172
7.9 Transfer Types ......................................................................................................................................... 173
7.9.1 Two-cycle transfer .......................................................................................................................173
7.9.2 Flyby transfer ...............................................................................................................................174
7.10 DMA Transfer Start Factors .................................................................................................................... 175
7.11 Terminal Count Output When DMA Transfer Is Complete ................................................................... 176
7.12 Forcible Interruption................................................................................................................................ 177
7.13 Forcible Termination ............................................................................................................................... 178
7.14 DMA Transfer Timing Examples............................................................................................................. 180
7.15 Precautions .............................................................................................................................................. 204
CHAPTER 8 INTC.....................................................................................................................................206
8.1 Features.................................................................................................................................................... 206
8.2 Non-Maskable Interrupts (NMI)............................................................................................................... 209
8.2.1 Operation .....................................................................................................................................212
8.2.2 Restore ........................................................................................................................................213
8.3 Maskable Interrupts................................................................................................................................. 214
8.3.1 Operation .....................................................................................................................................214
8.3.2 Restore ........................................................................................................................................216
8.3.3 Maskable interrupt priorities.........................................................................................................217
8.3.4 Control registers ..........................................................................................................................221
8.3.5 Maskable interrupt status flag (ID)...............................................................................................224
8.4 Software Exception ................................................................................................................................. 225
8.4.1 Operation .....................................................................................................................................225
8.4.2 Restore ........................................................................................................................................226
8.5 Exception Trap......................................................................................................................................... 227
8.5.1 Illegal opcode...............................................................................................................................227
8.5.2 Operation .....................................................................................................................................228
8.5.3 Restore ........................................................................................................................................228
8.6 Interrupt Response Time ........................................................................................................................ 229
Preliminary User's Manual A14874EJ3V0UM
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