Software Stop Mode - Renesas NU85E Preliminary User's Manual

6.4 Software STOP Mode

In software STOP mode, the CPU operation clock and the clock generator are stopped. The overall system is
stopped, and ultra-low power consumption is achieved in which only leak current is lost.
(1) Setting and operation status
The NU85E is switched to software STOP mode by using a store instruction (ST or SST instruction) or bit
manipulation instruction (SET1, CLR1, or NOT1 instruction) to set the PSC register.
Although program execution stops in software STOP mode, the contents of all registers and of RAM immediately
before software STOP mode began are maintained. The operation of all NU85E-internal peripheral I/O is also
stopped.
(2) Cancellation of software STOP mode
Software STOP mode is canceled by a non-maskable interrupt request, an unmasked maskable interrupt
request, or the input of a DCRESZ signal.
(a) Cancellation by interrupt request
Software STOP mode is canceled by a non-maskable interrupt request not masked by the PSC register or
by an unmasked maskable interrupt request regardless of the priority. The following table shows the
operation performed after software STOP mode is canceled.
Caution An interrupt request that occurs while the NMI2M to NMI0M and INTM bits of the power save
control resister (PSC) are set (interrupt disabled), is invalid (software STOP mode is not
canceled).
Table 6-2. Operation After Software STOP Mode Is Canceled by Interrupt Request
Cancellation Source
Non-maskable interrupt
request
Maskable interrupt request
The operation shown in Table 6-3 is performed if software STOP mode was set within the interrupt servicing
routine.
CHAPTER 6 STBC
Interrupt Enabled (EI) State
Branch to handler address
Branch to handler address or
execution of next instruction
Preliminary User's Manual A14874EJ3V0UM
Interrupt Disabled (DI) State
Execution of next instruction
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