Renesas NU85E Preliminary User's Manual page 194

(2) Flyby transfers
Figures 7-36 to 7-41 show examples of the timing of flyby transfers between external SRAM and external I/O
connected to the MEMC (NT85E500). The flyby transfer consists of the following states.
• T1, T2 states: These are basic states for accessing the NT85E500.
• T3 state:
This is a basic state added for flyby transfer.
• TA state:
This is an address setting wait state inserted by means of a setting in the NT85E500's ASC
register.
• TI state:
This is an idle state inserted by means of a setting in the NT85E500's BCC register.
• TW state:
This is a wait state inserted by means of a setting in the NT85E500's DWC0 register.
Remarks 1. The levels of the broken-line portions of the VMCTYP2 to VMCTYP0, VMSEQ2 to VMSEQ0,
VMSIZE1, VMSIZE0, and DI31 to DI0 signals indicate the undefined state.
2. n = 3 to 0
Figure 7-36 shows an example of the timing of a flyby single transfer (from external SRAM to external I/O
connected to the NT85E500). The settings of the registers in this figure are as follows.
[Register settings]
• DBCn register = 0001H (2 transfers)
• ASC register
Note
= FFEFH (CS2 address setting wait states = 2)
• BCC register Note
= FFEFH (CS2 idle states = 2)
• DWC0 register
Note
= 7377H (CS2 wait states = 3)
Note An NT85E500 register.
192
CHAPTER 7 DMAC
Preliminary User's Manual A14874EJ3V0UM