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The DMA control unit (DMAC) controls data transfers between memory and peripheral macros or between memory
and memory based on DMA transfer requests issued according to the DMARQ3 to DMARQ0 pins or software triggers
(memory means RAM or external memory).
7.1 Features
• Four independent DMA channels
• Transfer units: 8 bits, 16 bits, or 32 bits
• Maximum transfer count: 65,536 (2
• Two transfer types
Flyby (1-cycle) transfer
Two-cycle transfer
• Four transfer modes
Single transfer mode
Single-step transfer mode
Line transfer mode (four bus cycle transfer mode)
(in 2-cycle transfer, the operation from read to write is repeated four times)
Block transfer mode
• Transfer requests
Requests by DMARQ3 to DMARQ0 pin input
Requests by software
• Transfer objects
Note
Between RAM
and peripheral macros
Note
Between RAM
and external memory
Note
Between RAM
and RAM
Between external memory and peripheral macros
Between external memory and external memory (Transfer between little endian area and big endian area is
possible)
Note RAM directly connected to the VDB (refer to 7.2 Configuration)
• Terminal count output signals (DMTCO3 to DMTCO0)
• Next address setting function
CHAPTER 7 DMAC
16
)
Note
Preliminary User's Manual A14874EJ3V0UM
149
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