Halt Mode - Renesas NU85E Preliminary User's Manual

6.3 HALT Mode

In HALT mode, the operation clock of the CPU is stopped. Since the supply of clocks to internal units other than
the CPU continues, operation continues. The power consumption of the overall system can be reduced by setting
the NU85E to HALT mode while the CPU is idle.
(1) Setting and operation status
The NU85E is switched to HALT mode by the HALT instruction.
Although program execution stops in HALT mode, the contents of all registers and of RAM immediately before
HALT mode began are maintained. Also, operation continues for all NU85E-internal peripheral I/O that does not
depend on CPU instruction processing.
Caution Insert at least five NOP instructions after the HALT instruction.
(2) Cancellation of HALT mode
HALT mode is canceled by a non-maskable interrupt request, an unmasked maskable interrupt request, or the
input of the DCRESZ signal.
(a) Cancellation by interrupt request
HALT mode is canceled by a non-maskable interrupt request or by an unmasked maskable interrupt request
regardless of the priority. The following table shows the operation performed after HALT mode is canceled.
Table 6-1. Operation After HALT Mode Is Canceled by Interrupt Request
Cancellation Source
Non-maskable interrupt
request
Maskable interrupt request
The operation differs as follows if HALT mode was set within the interrupt servicing routine.
<1> When a low priority interrupt request is generated
Only HALT mode is canceled. The interrupt request is not acknowledged (pending).
<2> When a high priority interrupt request (including a non-maskable interrupt request) is
generated
HALT mode is canceled and the interrupt request is acknowledged.
(b) Cancellation by DCRESZ signal input
This is the same as a normal reset operation.
Caution Be sure to input the DCRESZ signal so that the setup and hold times referenced to the
VBCLK signal are satisfied.
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CHAPTER 6 STBC
Interrupt Enabled (EI) State
Branch to handler address
Branch to handler address or
execution of next instruction
Preliminary User's Manual A14874EJ3V0UM
Interrupt Disabled (DI) State
Execution of next instruction