Figure 6-6. Hardware STOP Mode Set/Cancel Timing Example
(a) When hardware STOP mode is canceled by DCSTOPZ input
clk
VBCLK (Input)
STPRQ (Output)
STPAK (Input)
HWSTOPRQ (Output)
DCSTOPZ (Input)
CGREL (Input)
(b) When hardware STOP mode is canceled by DCRESZ input
clk
VBCLK (Input)
STPRQ (Output)
STPAK (Input)
HWSTOPRQ (Output)
DCRESZ (Input)
DCSTOPZ (Input)
CGREL (Input)
Notes 1. Input a high level to the DCRESZ pin after restarting input of VBCLK.
2. Input a high level to the DCSTOPZ pin before inputting a high level to the DCRESZ pin.
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CHAPTER 6 STBC
Oscillation stabilization time
Oscillation stabilization time
Preliminary User's Manual A14874EJ3V0UM
1 clock or more
Note 1
Note 2
1 clock or more