Renesas NU85E Preliminary User's Manual page 35

(15) VMBSTR (output)
This pin outputs the burst read status indicating that the current transfer is opcode fetch from external ROM
when the NU85E has the bus access right and ROM connected as external memory (accessed via VSB) is used.
This pin operates with the same timing as the address bus.
(16) VMWAIT (input), VSWAIT (output)
These are wait response pins.
These signals are output to the bus master to request additional bus cycles when the selected bus slave has not
completed data output preparations. When these signals become high level, the bus cycle changes to the wait
status.
The NU85E uses the VMWAIT pin when it has the bus access right, and the VSWAIT pin when it operates as a
bus slave.
If a memory controller (MEMC) is connected to the NU85E, a high level is output to the VMWAIT pin of the
NU85E from MEMC while the VSB cycle occurs because the access cycle is always 2 or more clocks.
(17) VMLAST (input), VSLAST (output)
These are last response pins. These pins are used when the bus decoder requires a decode cycle.
In the case of a system where several slave devices are connected externally and a bus decoder has been
added to select slaves, decoding for bus slave selection is normally performed during non-sequential transfer.
Thus even when attempts to change a slave device are made during sequential transfer such as burst transfer,
the decode cycle for slave selection cannot be issued.
In such a case, the slave device outputs a last response notifying the fact that the slave selection signal has
changed to the bus master. When there is a last response from the slave device, the bus master makes the next
bus cycle non-sequential transfer to enable decode cycle issuance.
The NU85E uses the VMLAST pin to operate as the bus master, and the VSLAST pin when it operates as a bus
slave. The VSLAST pin, however, is fixed to low-level output and does not become active.
(18) VMAHLD (input), VSAHLD (output)
These are address hold response pins.
These signals are output to the bus master when the selected bus slave has completed data output preparations
and requests the bus cycle. When this signal and the VxWAIT signal become high level, the bus cycle goes into
the address hold status.
Since, in the address hold status, addresses do not change even during the data read and write cycles, there is
no need to latch addresses and the circuit can thus be kept simple.
The NU85E uses the VMAHLD pin when it has the bus access right, and the VSAHLD pin when it operates as a
bus slave. The VSAHLD pin, however, is fixed to low-level output and does not become active.
If a memory controller (MEMC) is connected to the NU85E, a high level is output to the NU85E from the MEMC
when an idle state is inserted.
(19) VDSELPZ (output), VSSELPZ (input)
These pins are used to output a low level to the bus slave when the bus master accesses a peripheral I/O area
or programmable peripheral I/O area.
The NU85E uses the VDSELPZ pin when it has the bus access right, and the VSSELPZ pin when it operates as
a bus slave.
CHAPTER 2 PIN FUNCTIONS
Preliminary User's Manual A14874EJ3V0UM
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